Backside Dielectric Pillar Air Gap for Lower Gate Capacitance
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing parasitic capacitance between neighboring gate structures due to difficulties in forming airgaps in the backside dielectric pillar between metal gate materials, leading to charge dissipation issues.
Innovation Solution
The formation of a pinched-off air gap within the backside dielectric pillar between metal gate materials, achieved through atomic layer deposition (ALD), which reduces parasitic capacitance by using a self-aligned backside dielectric pillar with defined pinched-off sections and sidewalls, thereby minimizing charge dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a backside dielectric pillar is formed between metal gate materials, then isolation between gates is achieved, but parasitic capacitance increases due to defective interfaces
Solution Approach 1:
The backside dielectric pillar is segmented into two distinct portions: a first portion with a first interface to the first metal gate material and a second portion with a second interface to the second metal gate material. This segmentation allows each interface to be independently optimized and controlled, reducing the formation of defective interfaces that cause parasitic capacitance while maintaining effective gate isolation.
2Object-generated harmful factors
If airgap is formed in backside dielectric pillar, then parasitic capacitance is reduced, but manufacturing complexity increases due to alignment requirements
Solution Approach 1:
The method performs preliminary actions by first forming the airgap structure and then subsequently forming the backside dielectric pillar around it. This sequence allows the airgap to be established as a template that guides the dielectric deposition, ensuring proper alignment and positioning without requiring complex real-time alignment procedures during pillar formation.
Solution Approach 2:
The airgap serves as an intermediary structure that mediates between the manufacturing process and the final device structure. By forming the airgap first and using it as a template for dielectric deposition, the method simplifies the overall manufacturing complexity while achieving the desired parasitic capacitance reduction.
3Manufacturing precision
If atomic layer deposition is used to form dielectric pillar, then manufacturing precision is improved, but process time increases
Solution Approach 1:
The atomic layer deposition process is applied in a controlled, partial manner by depositing dielectric material only in specific regions around the airgap structure. This selective deposition approach maintains the high manufacturing precision characteristic of ALD while reducing the total deposition time compared to forming a complete dielectric layer throughout the entire structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The pinched-off air gap effectively reduces parasitic capacitance, enhancing the overall performance of the semiconductor device by preventing charge dissipation at defective interfaces, making it suitable for complementary-metal-oxide-semiconductor (CMOS) compatibility and enabling backside power distribution networks.
Implementation Method 1
executing atomic layer deposition (ALD) to partially fill the first opening with dielectric defining a pinched-off air gap therein and to partially fill the second opening with the dielectric defining a partially pinched-off air gap therein
Data Source
AI summary
A semiconductor device is provided and includes first and second active regions, a shared gate structure disposed across the first and second active regions and including first and second metal gate material in the first and second active regions, respectively, a self-aligned backside dielectric pillar interposed between a first portion of the first metal gate material and a first portion of the second metal gate material and a shared gate plug interposed between a second portion of the first metal gate material and a second portion of the second metal gate material. The self-aligned backside dielectric pillar defines a pinched-off air gap extending across a width-wise portion of the self-aligned backside dielectric pillar and along a height-wise portion of the self-aligned backside dielectric pillar.