Backside-Terminal P-I-N Diode Layout for ESD Current Shunting
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Solution Overview
Problem
Electrostatic discharge (ESD) can cause failures in electronic devices, and existing ESD protection circuits often include diodes and clamping circuits that may not effectively protect internal components from damage.
Innovation Solution
The implementation of P-Intrinsic-N (P-I-N) diodes in a bulk-less process, such as silicon-on-insulator (SOI) or super power rail (SPR), with frontside and backside conductive layers connected through vias, and the use of power-rail clamping circuits to shunt ESD current, bypassing internal circuit victims.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional diodes and clamping circuits are used in ESD protection circuits, then the circuit structure is simple, but the protection effectiveness against ESD is insufficient
Solution Approach 1:
The ESD protection circuit is segmented into multiple functional regions: a first region with a first P-I-N diode for first ESD events, and a second region with a second P-I-N diode for second ESD events. Each region independently handles specific ESD scenarios, improving overall protection effectiveness while maintaining manageable circuit complexity through modular design
Solution Approach 2:
The circuit utilizes different breakdown voltage parameters for the first and second P-I-N diodes to handle different ESD event characteristics. By changing the voltage threshold parameter, the circuit can selectively activate appropriate protection paths for different ESD scenarios, enhancing protection effectiveness without requiring completely different circuit topologies
2Reliability
If P-I-N diodes are implemented in bulk-less process with backside terminals, then ESD current shunting capability is improved, but manufacturing complexity increases
Solution Approach 1:
The P-I-N diodes are implemented in a bulk-less process using silicon-on-insulator (SOI) technology, transitioning from three-dimensional bulk semiconductor to a planar, layered structure. This dimensional change enables better ESD current shunting by providing dedicated frontside and backside contact regions while simplifying the manufacturing process through standard SOI fabrication techniques
Solution Approach 2:
An intrinsic region is introduced as an intermediary layer between the P-type and N-type doped regions in the P-I-N diode structure. This intrinsic layer acts as a mediator that facilitates controlled breakdown and ESD current shunting, enabling effective protection in bulk-less processes where traditional bulk semiconductor mechanisms are unavailable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The P-I-N diodes effectively protect internal circuits by shunting ESD current, preventing damage and ensuring the reliability of electronic devices.
Implementation Method 1
Sometimes, electrostatic discharge (ESD) causes failures in electronic devices
Implementation Method 2
The intrinsic region is electrically connected to the P-type doped region and the N-type doped region
Data Source
AI summary
A device including a substrate having a frontside and a backside, a first P-I-N diode situated on the frontside of the substrate, a first terminal situated under the backside of the substrate, a plurality of frontside conductive layers, and a plurality of backside conductive layers. The plurality of frontside conductive layers situated over the first P-I-N diode and electrically connected to the first P-I-N diode. The plurality of backside conductive layers situated under the backside of the substrate and electrically connected to the first terminal that is electrically connected to the first P-I-N diode through the plurality of backside conductive layers and at least one via.