Semiconductor Backside Plating Structure for High Planarity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high planarity on the back surface where through electrodes are exposed, leading to variations in thickness and difficulties in coupling with other substrates, which affects handleability and performance.
Innovation Solution
A semiconductor device configuration that includes a semiconductor substrate with a first and second plating film pattern, and an insulating layer, where the plating film patterns have a two-layer structure with specific coverage areas and are electrically separate, filled with a planarizing film to achieve high planarity and improved handleability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single-layer plating film is used on the back surface, then the manufacturing process is simple, but the planarity and thickness uniformity are insufficient
Solution Approach 1:
The plating film is divided into multiple layers (first plating film layer and second plating film layer) with different materials and functions. The first layer provides base conductivity and adhesion, while the second layer enhances planarity and prevents dishing, resolving the contradiction between manufacturing precision and device complexity.
Solution Approach 2:
The patent uses composite plating film structures combining different materials (e.g., Cu/W, Cu/Mo, Cu/ Ru) where each material contributes specific properties. This composite approach achieves superior planarity and thickness uniformity compared to single-layer films, addressing the manufacturing precision requirement.
2Manufacturing precision
If a thick plating film is applied to ensure coverage, then the conductivity is sufficient, but dishing occurs and planarity deteriorates
Solution Approach 1:
The plating film is segmented into multiple thin layers instead of one thick layer. Each layer is deposited separately with controlled thickness, preventing dishing while ensuring adequate coverage and conductivity. The cumulative effect of multiple thin layers maintains film integrity without causing planarity issues.
Solution Approach 2:
The patent changes the deposition parameters by controlling the thickness of each individual layer to be thinner than the single thick layer would be. This parameter adjustment prevents dishing during deposition while maintaining the necessary electrical conductivity and mechanical strength through the combined structure.
3Ease of operation
If the back surface is used for coupling without additional processing, then the manufacturing process is short, but the handleability and coupling accuracy are poor
Solution Approach 1:
The plating film structure is preliminarily formed during the semiconductor manufacturing process itself, creating a ready-to-use coupling surface with high planarity and appropriate electrical properties. This preliminary action eliminates the need for additional post-processing steps, improving handleability without extending the manufacturing cycle.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The configuration enhances planarity, reduces thickness variations, prevents dishing of the plating film, and allows for efficient coupling with other substrates, improving the semiconductor device's handleability and manufacturing productivity.
Implementation Method 1
a first plating film pattern that includes a first portion and a second portion, the first portion covering a first regional portion of the first surface, the second portion being stacked to cover a portion of the first portion
Data Source
AI summary
Provided is a semiconductor device having high planarity in an in-plane direction. This semiconductor device includes a semiconductor substrate, a first plating film pattern, a second plating film pattern, and an insulating layer. The semiconductor substrate has a first surface, and a second surface on a side opposite to the first surface. The first plating film pattern includes a first portion that covers a first regional portion of the first surface, and a second portion that is stacked to cover a portion of the first portion. The second plating film pattern includes a third portion that covers a second regional portion different from the first regional portion of the first surface, and also includes a fourth portion that is stacked to cover a portion of the third portion. A portion between the second portion and the fourth portion is filled with the insulating layer.