Backside Plug-Last IC Contacts for Uniform Etch and Lower Resistance
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits faces challenges due to variability in conventional fabrication processes, leading to difficulties in extending these processes beyond the 10 nanometer node, with issues such as etch loading effects in backside trench contact formation and high electrical resistance in power delivery networks.
Innovation Solution
A plug last approach is adopted for backside trench contact etch, where a backside trench contact grating is etched into the substrate, followed by plug patterning and filling, to eliminate etch loading effects and ensure uniformity, and power is delivered from the wafer backside to reduce interconnect stress and improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for backside trench contact formation, then manufacturing simplicity is maintained, but etch loading effects occur and manufacturing precision deteriorates
Solution Approach 1:
The patent inverts the conventional fabrication sequence by performing plug patterning and filling before backside trench contact etching. This reversal eliminates etch loading effects that occur when trenches are etched first, resulting in uniform poly profiles and improved manufacturing precision without significantly increasing overall process complexity.
Solution Approach 2:
The patent performs preliminary plug patterning and filling actions before the backside trench contact etching step. By establishing the plug structures in advance, the subsequent etching process proceeds without loading effects, ensuring uniform poly profiles and resolving the precision issue.
2Reliability
If power is delivered from the front side of the wafer, then interconnect routing is simpler, but power network resistance increases and performance deteriorates
Solution Approach 1:
The patent transitions power delivery from the conventional front-side (two-dimensional planar routing) to the backside of the wafer (utilizing the third dimension through substrate thickness). This dimensional change enables shorter current paths and reduced interconnect resistance, improving power delivery performance while the plug structures manage the increased structural complexity.
3Productivity
If multi-gate transistor dimensions are scaled down to increase device density, then functional unit density increases, but process variability increases and manufacturing precision deteriorates
Solution Approach 1:
The patent inverts the fabrication sequence to perform plug patterning before trench etching, which eliminates etch loading effects. This inversion maintains uniform poly profiles even as transistor dimensions are scaled down, thereby reducing process variability and improving manufacturing precision while preserving high device density.
Data Source
AI summary
Integrated circuit structures having backside plug last approach are described. In an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires or a fin. A gate stack is over the plurality of horizontally stacked nanowires or the fin. A conductive trench contact structure is at a level below the plurality of horizontally stacked nanowires or the fin, the conductive trench contact structure having outwardly tapered sidewalls from a top of the conductive trench contact structure to a bottom of the conductive trench contact structure.