Backside PMOS Epitaxial Contact Layout for Lower SRAM VCC Drop

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Solution Overview

Problem

Legacy SRAM designs require multiple front side metal layers for connecting PMOS epitaxial structures to SVCC, leading to resistive voltage drops, inefficient routing, and increased word line and bit line capacitance, which affects SRAM performance.

Innovation Solution

Direct electrical coupling of PMOS and NMOS epitaxial structures with backside contact metals, reducing the need for front side connections and minimizing resistive voltage drops and capacitance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple front side metal layers are used to connect PMOS epitaxial structures to SVCC, then electrical connections can be established, but resistive voltage drops increase and routing efficiency decreases

Engineering Contradiction:

Improveelectrical connection reliabilityVSAvoidresistive voltage drop

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent moves the electrical connection from the front side (2D plane) to the back side of the substrate, utilizing the third dimension (depth/substrate thickness) to create a more efficient current path. By forming back side contact metals that directly touch the PMOS epitaxial structures through the substrate, the current path is shortened and resistance is reduced, eliminating the need for multiple front side metal layers while improving electrical connection reliability.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If multiple front side metal layers are used for connecting PMOS epitaxial structures, then connections are established, but the number of connections and device complexity increases

Engineering Contradiction:

Improveelectrical connectionVSAvoidnumber of front side connections

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the electrical connection function from the front side metal layer structure and relocates it to the back side of the substrate. By taking out the connection requirement from the complex multi-layer front side routing and implementing it through simple back side contact metals, the device complexity is significantly reduced while maintaining reliable electrical connections between PMOS epitaxial structures and SVCC.

Inventive Principle:

Principle #2Taking out (Extraction)

3Reliability

If multiple front side metal layers are used, then electrical connections are established, but coupling capacitance between word line and bit line increases

Engineering Contradiction:

Improveelectrical connectionVSAvoidcoupling capacitance

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent removes the front side metal layers that were causing parasitic coupling capacitance between word lines and bit lines. By extracting this routing function and implementing connections through back side contact metals, the harmful capacitive coupling is eliminated, improving signal integrity and reducing interference while maintaining reliable electrical connections.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS12444685B2Backside electrical contact for PMOS epitaxial voltage supply

Publication Date: 2025.10.14 INTEL CORP

AI summary

Embodiments described herein may be related to apparatuses, processes, systems, and techniques directed to electrical couplings between epitaxial structures and voltage sources within transistors in SRAM bit cells. Embodiments include direct electrical couplings between a backside contact metal (BM0) and a backside of an epitaxial structure to provide SRAM VCC voltage (SVCC) voltage, as well as electrical connection structures that electrically couple the BM0 to a front side of an epitaxial structure to provide SVCC voltage. Other embodiments may be described and/or claimed.