Semiconductor Backside Polymer Stripes for Crack-Free Dicing
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Solution Overview
Problem
The cost-intensive process of packaging semiconductor chips remains a challenge in semiconductor device manufacturing, particularly due to high expenses associated with conventional dicing methods that can lead to chip crack propagation and chipping during separation.
Innovation Solution
The method involves forming polymer stripes on the backside of a semiconductor wafer, applying a conductive layer, and planarizing it to create a structured backside metallization, which allows for efficient dicing using stealth dicing technology, reducing tensile stress and enabling the use of conventional dicing methods like sawing or laser dicing while protecting chip edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional dicing methods (sawing or laser dicing) are used to separate semiconductor chips, then chip separation can be achieved, but tensile stress causes chip crack propagation and chipping during separation
Solution Approach 1:
The patent applies preliminary action by forming a stress relief structure (groove or cavity) in the semiconductor substrate before the dicing process. This pre-formed structure reduces tensile stress during subsequent chip separation, preventing crack propagation and chipping while enabling efficient conventional dicing methods to be used.
2Reliability
If stealth dicing technology is used to reduce tensile stress, then chip crack propagation is minimized, but the process complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the semiconductor substrate into individual chip regions using a dicing saw that follows predetermined scribe lines. The stress relief structure is also segmented, with grooves or cavities positioned between adjacent chips to independently manage stress in each region, simplifying the overall dicing process while maintaining chip integrity.
3Productivity
If polymer stripes are formed on the backside of the wafer and conductive layer is applied, then structured backside metallization is created for efficient dicing, but manufacturing steps increase
Solution Approach 1:
The patent applies multi-functionality by creating a stress relief structure that serves multiple purposes: it reduces tensile stress during dicing, provides a pathway for the dicing saw blade, and can be integrated with existing semiconductor fabrication processes. The conductive layer and polymer stripes serve both as structural elements for stress management and as part of the electrical interconnection system.
Data Source
AI summary
A semiconductor device includes a semiconductor chip including a first main face and a second main face wherein the second main face is the backside of the semiconductor chip. Further, the semiconductor device includes an electrically conductive layer, in particular an electrically conductive layer, arranged on a first region of the second main face of the semiconductor chip. Further, the semiconductor device includes a polymer structure arranged on a second region of the second main face of the semiconductor chip, wherein the second region is a peripheral region of the second main face of the semiconductor chip and the first region is adjacent to the second region.