Back-Side Power Delivery in 3D DRAM Packaging to Cut Voltage Drop

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing semiconductor packaging methods using Through-Silicon Vias (TSVs) for connecting 3D stacked Dynamic Random Access Memory (DRAM) chips with a System on Chip (SoC) result in higher process costs and lower performance due to front-side power supply transmission, leading to voltage drop and increased delay times.

Innovation Solution

A semiconductor packaging method employing a back-side power supply transmission mode, where interconnection structures are formed on both sides of a driver layer, allowing simultaneous preparation and electrical connection, reducing the size and cost of the interconnection structure, and improving production efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If Through-Silicon Vias (TSVs) are used to connect 3D stacked DRAM chips with SoC using front-side power supply transmission, then electrical connection is achieved, but voltage drop increases and delay time increases

Engineering Contradiction:

Improveelectrical connection qualityVSAvoidvoltage drop

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent inverts the traditional front-side power supply transmission approach by implementing back-side power supply transmission. The power supply circuit is placed on the back side of the driver layer, and power is transmitted through the back side interconnection structure, reversing the conventional current path and reducing voltage drop across the chip.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent transitions from two-dimensional front-side interconnection to three-dimensional interconnection by utilizing both the front side and back side of the driver layer. This spatial dimensionality change allows power and signal transmission through different layers, optimizing electrical performance.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If Through-Silicon Vias (TSVs) are used to connect 3D stacked DRAM chips with SoC, then electrical connection is achieved, but process cost increases

Engineering Contradiction:

Improveelectrical connection qualityVSAvoidprocess cost

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent segments the interconnection function into two independent parts: front side interconnection structure for signal transmission and back side interconnection structure for power supply. This segmentation eliminates the need for complex TSV processes, simplifying manufacturing and reducing costs.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent extracts the power supply transmission function from the front side interconnection structure and places it on the back side. This extraction simplifies the front side structure and eliminates the need for TSVs, reducing process complexity and cost.

Inventive Principle:

Principle #2Taking out (Extraction)

3Ease of manufacture

If layer-by-layer preparation method is used for interconnection structures, then manufacturing is simplified, but production efficiency decreases

Engineering Contradiction:

Improvemanufacturing simplicityVSAvoidproduction efficiency

Core Design Contradiction:

Ease of manufactureVSProductivity

Solution Approach 1:

The patent forms both the front side interconnection structure and the back side interconnection structure simultaneously during the same manufacturing process steps, rather than sequentially. This preliminary action on both sides at once significantly improves production efficiency while maintaining manufacturing simplicity.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250329700A1Semiconductor packaging method, semiconductor assembly component and electronic device

Publication Date: 2025.10.23 SHANGHAI YIBU SEMICON CO LTD

AI summary

A semiconductor packaging method adopts a back-side power supply transmission mode, and includes a first interconnection structure and a second interconnection structure on one side of a driver layer, and a third interconnection structure on an opposite side of the driver layer. The driver layer transmits driving signals to a semiconductor device through the first interconnection structure and the second interconnection structure. The driver layer is electrically connected to the third interconnection structure, and the third interconnection structure is used for transmitting a voltage to the driver layer. As a result, the sizes of the interconnection structures are reduced, reducing costs and improving over problems such as voltage drop and delay time. Meanwhile, compared with the layer-by-layer preparation methods, the first interconnection structure and the second interconnection structure can be prepared separately and concurrently before being electrically connected, resulting in shortened packaging time and improved production efficiency.