Backside Power Delivery Structure With Air-Gap Isolation

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Solution Overview

Problem

The increasing demand for high-performance semiconductor devices with high integration and multifunctionality poses challenges in developing effective power delivery networks and electrical characteristics, particularly in devices with BackSide Power Delivery Network (BSPDN) structures.

Innovation Solution

The semiconductor device incorporates a substrate insulating layer with protruding insulating patterns, gate structures overlapping these patterns, and separation patterns with air gaps and insulating liners to enhance electrical insulation and power delivery, utilizing a backside contact structure for improved electrical connectivity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If power rails are disposed on the backside of the wafer to achieve high integration, then device functionality is improved, but parasitic voltage increases and electrical characteristics deteriorate

Engineering Contradiction:

Improvedevice functionalityVSAvoidparasitic voltage

Core Design Contradiction:

Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

The power delivery network is segmented into multiple independent power rails disposed on the backside of the wafer, allowing each rail to be independently controlled and optimized. This segmentation reduces parasitic voltage by preventing current crowding and enabling better current distribution across the device.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The power delivery network transitions from a planar configuration to a three-dimensional structure by disposing power rails on the backside of the wafer. This dimensional change enables shorter current paths, reduced inductance, and improved power delivery efficiency while maintaining high integration.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Productivity

If the degree of integration is increased to meet high performance demands, then device capability is improved, but electrical characteristics and power delivery efficiency deteriorate

Engineering Contradiction:

Improvedevice capabilityVSAvoidpower delivery efficiency

Core Design Contradiction:

ProductivityVSLoss of energy

Solution Approach 1:

The power delivery network is inverted by placing power rails on the backside of the wafer rather than on the frontside. This inversion shortens the current paths between power sources and active devices, reducing resistive losses and improving power delivery efficiency despite increased integration density.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The backside of the wafer serves as an intermediary platform for the power delivery network, enabling direct connection between power sources and devices without interfering with the frontside circuit layout. This intermediary structure reduces power loss and improves efficiency.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces parasitic voltage and enhances the reliability and electrical characteristics of semiconductor devices by improving power delivery and insulation, thereby supporting high integration and multifunctionality.

Implementation Method 1

at least one of the first separation pattern and the plurality of second separation patterns includes an air gap and an insulating liner

Methodology Applied

Scientific EffectElectrical insulation: Dielectric

Implementation Method 2

This configuration reduces parasitic voltage and enhances the reliability and electrical characteristics

Methodology Applied

Scientific EffectParasitic capacitance reduction: Parasitic Capacitance

Implementation Method 3

a backside contact structure that extends into the substrate insulating layer, wherein the backside contact structure is electrically connected to at least one of the plurality of source/drain regions

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS20260026091A1Semiconductor devices comprising backside power delivery network structure

Publication Date: 2026.01.22 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor device includes a substrate insulating layer including an insulating pattern, a first gate structure and a second gate structure overlapping the insulating pattern, first semiconductor patterns spaced apart from each other and second semiconductor patterns spaced apart from each other, first and second source/drain regions respectively connected to the first and second semiconductor patterns, a first separation pattern extending between the first and second gate structures, the first separation pattern insulating the first and second gate structures from each other, a second separation pattern extending into respective at least portions of ones of the first semiconductor patterns and ones of the second semiconductor patterns, and a backside contact plug extending into the substrate insulating layer and connected to at least some of the source/drain regions. At least one of the first and second separation patterns includes an air gap.