Backside Power Alignment Marks for Source/Drain Connections
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Solution Overview
Problem
Current semiconductor manufacturing processes face challenges in aligning source/drain and power line connections effectively, particularly when transitioning the power delivery network from the front side to the backside of a semiconductor wafer, which affects the efficiency and reliability of backside power connections.
Innovation Solution
The development of a semiconductor device with a conductive alignment region and backside interconnects that allow for direct backside source/drain connections to a backside power delivery network, utilizing shallow through-silicon vias and alignment vias formed during middle-of-line processing, enabling easy backside contact patterning and alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power delivery network is moved from front side to backside of semiconductor wafer, then power connection reliability is improved, but alignment precision deteriorates
Solution Approach 1:
Alignment marks are formed on the front side of the substrate during front-end-of-line processing, before the substrate is flipped to the back side. These pre-formed alignment marks serve as reference features that guide subsequent backside power connection formation, ensuring precise alignment is achieved despite the side transition.
Solution Approach 2:
The alignment marks are essentially copies or projections of front-side features that are used to transfer positional information to the back side. By creating visible alignment references on the front side that correspond to backside target locations, the system copies spatial relationships across the substrate flip operation.
2Device complexity
If shallow through-silicon vias are used for backside connections, then manufacturing complexity is reduced, but connection reliability may worsen
Solution Approach 1:
The via depth is changed from deep through-silicon vias to shallow through-silicon vias, modifying the geometric parameter of the connection structure. This parameter change simplifies the manufacturing process while the alignment mark system compensates to maintain connection reliability through improved positioning accuracy.
3Ease of operation
If substrate is inverted for backside processing, then ease of operation is improved, but alignment precision deteriorates
Solution Approach 1:
Alignment marks are formed on the front side before substrate inversion, serving as pre-established reference features that remain in known positions relative to device structures. This preliminary action ensures that when the substrate is flipped for backside processing, the alignment references are already in place to guide precise backside operations.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a first source/drain of a first semiconductor device, and a second source/drain of a second semiconductor device. The semiconductor device further includes a source/drain contact adjoining a first side of the first source/drain, a frontside via adjoining the source/drain contact, and a backside electric contact adjoining a first side of the second source/drain, wherein the backside electric contact is on a side opposite the source/drain contact, and a conductive alignment region. The device further includes a backside interconnect electrically connected to the conductive alignment region, wherein the backside interconnect is on the same side of the first and second source/drain as the backside electric contact, and an alignment region via electrically connected to the conductive alignment region, wherein the alignment region via is on the same side of the first and second source/drain as the source/drain contact and frontside via.