Back-Side Power Delivery for Backend Memory Leakage and Density
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Solution Overview
Problem
Conventional 1T-1C memory cells face challenges in advanced technology nodes due to leakage issues with logic transistors, capacitor scaling, and density limitations when using frontend transistors, making it difficult to achieve low power and high density embedded memory.
Innovation Solution
Implementing backend memory using thin-film transistors (TFTs) or layer transfer to form access transistors in the BEOL layer, and providing power to these memory cells from the back side of the IC device through back-side reveal, which allows for easier fabrication and reduced complexity in power routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frontend transistors are used in conventional 1T-1C memory cells, then logic functionality is achieved, but leakage increases and density is limited in advanced technology nodes
Solution Approach 1:
The patent divides the transistor fabrication into two separate stages: frontend transistors (logic) and backend transistors (memory). This segmentation allows each stage to be optimized independently, with backend TFTs achieving lower leakage while maintaining high density through the stacked architecture.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional stacked architecture, placing backend memory TFTs above frontend logic transistors. This vertical dimension enables higher density while separating the leakage characteristics of logic and memory transistors.
2Productivity
If capacitor size is scaled down to increase density, then more memory cells fit in the same area, but capacitance decreases and leakage increases
Solution Approach 1:
The patent moves capacitor formation to the backend process stage, allowing capacitors to be integrated in the vertical stack above the frontend logic layer. This three-dimensional integration maintains sufficient capacitance values while achieving higher overall memory density.
3Device complexity
If power is routed from the front side to backend memory, then conventional routing is used, but routing complexity and parasitic effects increase
Solution Approach 1:
The patent inverts the conventional power routing approach by delivering power from the back side of the substrate to the backend memory TFTs, rather than routing power from the front side through multiple interconnect layers. This back-side power delivery reduces routing complexity and minimizes parasitic inductance and resistance.
Data Source
AI summary
Embodiments of the present disclosure provide power to backend memory of an IC device from the back side of the device. An example IC device with back-side power delivery for backend memory includes a frontend layer with a plurality of frontend components such as frontend transistors, a backend layer (that may include a plurality of layers) with backend memory (e.g., with one or more eDRAM arrays), and a back-side power delivery structure with a plurality of back-side interconnects electrically coupled to the backend memory, where the frontend layer is between the back-side power delivery structure and the backend layer.