Backside Power Bar Gate Tie-Down for Low-Resistance CMOS Contacts
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Solution Overview
Problem
Conventional CMOS integrated circuit manufacturing involves high-aspect-ratio etches and dielectric fills, increasing production costs and complexity, and can damage adjacent source/drain regions.
Innovation Solution
A backside gate tie down is achieved through a backside power bar, connecting the power rail to the source/drain and gate regions from the backside of the wafer, avoiding deep frontside etches and reducing the risk of gate shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SDB technology is used to isolate regions, then gate isolation is achieved, but production costs and complexity increase due to multiple high-aspect-ratio etches and dielectric fill processes
Solution Approach 1:
The patent performs the gate tie-down connection from the backside of the wafer rather than the frontside. This inversion allows the power bar to be formed after the FET gates are completed on the frontside, eliminating the need for deep frontside etches and complex dielectric fills while achieving the same isolation function.
Solution Approach 2:
The connection is moved from the vertical dimension (deep frontside etches) to the horizontal dimension (backside wafer surface). By forming the power bar on the backside of the wafer, the patent avoids high-aspect-ratio etching and uses standard planar processing techniques instead.
2Reliability
If deep frontside etches are performed for power via connection, then gate tie down is achieved, but adjacent source/drain region epitaxial material is damaged
Solution Approach 1:
Instead of etching from the frontside where the delicate epitaxial source/drain regions are located, the patent performs the tie-down connection from the backside of the wafer. This approach completely avoids the harmful etching effects on the epitaxial material while achieving the same electrical connection.
Solution Approach 2:
The patent separates the gate tie-down function from the frontside FET structure by creating a distinct backside power bar. This segmentation allows the connection to be made without interfering with the frontside epitaxial regions, as the two operations occur on opposite sides of the wafer.
3Reliability
If backside power bar is formed to connect gate from backside, then contact resistance is reduced, but additional processing steps are required
Solution Approach 1:
The patent combines multiple functions into the backside power bar: it serves as both the power connection and the gate tie-down connection. By forming this single structure on the backside, the patent achieves low contact resistance while avoiding the need for separate deep frontside etching and dielectric fill operations.
Solution Approach 2:
The backside power bar is formed after the FET gates are completed on the frontside, but before final packaging. This timing allows the power bar to be self-aligned to the gate structures without requiring additional alignment steps, as the gate positions are already established from the frontside processing.
Data Source
AI summary
Techniques for forming backside gate tie down through a backside power bar are provided. In one aspect, a semiconductor device is provided, including: at least one FET (e.g., a first FET, a second FET, etc.) on a frontside of a wafer; a backside power rail on a backside of the wafer; and a backside power bar connecting the backside power rail to a source/drain region of the at least one FET from the frontside of the wafer and a gate of the at least one FET from the backside of the wafer. A method of fabricating a semiconductor device is also provided.