Backside Power Routing With Self-Aligned Buried Conductors

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Solution Overview

Problem

There is a need for a method to effectively dispose interconnections, such as power lines, on the backside of a semiconductor substrate and form conductive through-structures that penetrate the substrate to connect these interconnections in semiconductor devices like logic circuits and memories.

Innovation Solution

A semiconductor device is designed with fin-type active patterns, gate structures, separation structures, source/drain regions, an interlayer insulating layer, a contact structure, a buried conductive structure, and a power transmission structure. The buried conductive structure is self-aligned using adjacent separation structures and source/drain regions, extending vertically within the interlayer insulating layer, and the power transmission structure connects to the buried conductive structure from the backside of the substrate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If conductive through-structures are formed to penetrate the substrate for backside interconnection, then power transmission capability is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvepower transmission capabilityVSAvoidmanufacturing process complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The buried conductive structure is formed in advance within the interlayer insulating layer before substrate thinning and backside processing. This preliminary formation simplifies subsequent steps by providing pre-positioned conductive paths that align with separation structures, reducing the complexity of forming through-substrate connections later.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The buried conductive structure is nested within the interlayer insulating layer between separation structures, creating a hierarchical arrangement where conductive elements are embedded within insulating matrices. This nested configuration allows compact integration of power transmission paths without increasing overall device footprint or manufacturing complexity.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Ease of manufacture

If photolithography and etching processes are simplified, then manufacturing ease is improved, but manufacturing precision may worsen

Engineering Contradiction:
Improveprocess simplicityVSAvoidalignment precision
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

Separation structures serve as intermediary reference elements that define the positioning of buried conductive structures. By using these pre-formed separation structures as alignment references during subsequent photolithography steps, the patent achieves precise positioning without requiring complex alignment processes, thus maintaining both simplicity and precision.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The buried conductive structure is formed to be self-aligned with the separation structures through the preliminary action of forming conductive regions between predefined separation structures. This self-alignment mechanism eliminates the need for additional complex alignment steps, allowing the structure to automatically position itself relative to separation structures during formation.

Inventive Principle:
Principle #25Self-service

3Reliability

If contact resistance is reduced, then electrical performance is improved, but device complexity increases

Engineering Contradiction:
Improvecontact resistanceVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The buried conductive structure merges the functions of through-substrate vias and interlayer connections into a single continuous conductive path formed within the interlayer insulating layer. This merged structure reduces contact resistance by eliminating multiple interfaces while maintaining simplicity through the use of existing separation structures as alignment references.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentEP4439642A1Semiconductor device
Publication Date: 2024.10.02 SAMSUNG ELECTRONICS CO LTD
  • EP4439642A1 patent drawingFigure 1
  • EP4439642A1 patent drawingFigure 2
  • EP4439642A1 patent drawingFigure 3A

AI summary

Provided is a semiconductor device, the semiconductor device, including: a plurality of fin-type active patterns extending in a first direction on a substrate; a gate structure extending in a second direction, and crossing the plurality of fin-type active patterns; a plurality of separation structures extending in the second direction,; source/drain regions disposed on the plurality of fin-type active patterns on both sides of the gate structure; an interlayer insulating layer covering the source/drain regions on the substrate; a contact structure connected to at least one of the source/drain regions; a buried conductive structure electrically connected to the contact structure in the interlayer insulating layer, and having a first width defined by a distance between adjacent separation structures among the plurality of separation structures; and a power transmission structure extending from the second surface toward the first surface of the substrate, and connected to the buried conductive structure.