Backside Power Network Structure With Substrate Cavity for RC Delay
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Solution Overview
Problem
Integrated circuit devices face performance deterioration due to parasitic capacitance between backside contacts and placeholders, which increases resistive-capacitive (RC) delay, and existing methods to mitigate this require additional processes like lithography and etching.
Innovation Solution
A cavity is formed in the substrate between backside contacts and placeholders, reducing parasitic capacitance without the need for additional processes, thereby improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If backside contacts and placeholders are formed in the substrate, then power distribution is improved, but parasitic capacitance increases causing RC delay
Solution Approach 1:
The harmful substrate material is extracted/removed from the region between backside contacts and placeholders by forming a cavity. This removes the dielectric material that causes parasitic capacitance, thereby reducing RC delay while maintaining the power distribution function of the backside contacts and placeholders.
Solution Approach 2:
A cavity (void space) is created in the substrate between backside contacts and placeholders. This porous/void structure eliminates the dielectric material that causes parasitic capacitance, reducing RC delay while allowing the backside power distribution network to function effectively.
2Loss of time
If additional processes like lithography and etching are used to mitigate parasitic capacitance, then RC delay is reduced, but device complexity and manufacturing steps increase
Solution Approach 1:
The cavity formation process is merged with the existing substrate preparation steps. The cavity is formed as part of the substrate structure itself, combining the cavity formation with the substrate fabrication process, thereby reducing RC delay without adding separate lithography and etching steps.
Solution Approach 2:
The substrate structure itself provides the solution by incorporating the cavity during substrate formation. The substrate serves dual purposes: providing mechanical support and creating the parasitic capacitance-reducing cavity structure, eliminating the need for additional corrective processes.
Data Source
AI summary
Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include a transistor including first and second source/drain regions spaced apart from each other in a horizontal direction, a backside power distribution network structure (BSPDNS), a substrate between the first and second source/drain regions and the BSPDNS, a backside contact that is in the substrate and is overlapped by the first source/drain region, a placeholder that is in the substrate and is overlapped by the second source/drain region, and a cavity in the substrate between the backside contact and the placeholder.