Backside Power Contact Layout for Self-Aligned Source/Drain Access
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Solution Overview
Problem
The increasing complexity and density of semiconductor integrated circuits (ICs) result in higher power dissipation and performance issues due to misalignment of power conductive contacts with source/drain regions, leading to unwanted connections and increased resistance, which affects processing power and speed.
Innovation Solution
A metal line routing method is employed where power conductive contacts are formed on the wafer back-side, self-aligning with the source/drain regions through a stepped sidewall structure, allowing for improved contact resistance and reduced routing loading by using a back-side power mesh at a lower metal layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power conductive contacts are formed on the front side of the wafer, then routing loading is reduced, but misalignment with source/drain regions occurs leading to unwanted connections and increased resistance
Solution Approach 1:
The patent inverts the conventional approach by forming power conductive contacts on the back side of the wafer instead of the front side. This inversion allows the contacts to self-align with the source/drain regions through the substrate, eliminating alignment issues and unwanted connections while still achieving reduced routing loading on the front side.
Solution Approach 2:
The patent moves the power conductive contacts from the traditional planar dimension (front side surface) to a different spatial dimension (back side of the substrate). This dimensional change enables the contacts to penetrate through the substrate and directly connect with source/drain regions, achieving both precise alignment and reduced routing loading.
2Productivity
If geometry size is scaled down to increase functional density, then production efficiency increases, but power dissipation increases
Solution Approach 1:
The patent segments the power delivery path into separate front-side and back-side components. The back-side power conductive contacts handle power delivery to source/drain regions, while the front side focuses on signal routing. This segmentation allows continued scaling for higher functional density while the optimized power path manages power dissipation more effectively.
Solution Approach 2:
The substrate acts as an intermediary medium that enables direct vertical connection between back-side power contacts and source/drain regions. This intermediary structure provides a low-resistance power delivery path that scales with device geometry, allowing functional density to increase while power dissipation is managed through the efficient intermediary connection.
3Ease of manufacture
If power conductive contacts are misaligned with source/drain regions, then manufacturing is simpler, but unwanted connections and increased resistance occur
Solution Approach 1:
The back-side contact formation process is self-aligning, where the contact automatically positions itself relative to the source/drain regions through the substrate. This self-service mechanism eliminates the need for complex alignment procedures while ensuring accurate connection, thereby maintaining ease of manufacture while dramatically improving connection accuracy and reliability.
Data Source
AI summary
A method includes forming a semiconductive sheet over a front-side of a semiconductive region that is on a front-side of a substrate; forming semiconductive layers on the front-side of the semiconductive region and at either side of the semiconductive sheet; forming source/drain structures over the semiconductive layers and on the either side of the semiconductive sheet; forming a gate structure wrapping around the semiconductive sheet; performing a planarization process on a back-side of the substrate to expose the semiconductive region; etching the semiconductive region from a back-side of the semiconductive region to form a first opening exposing a first one of the semiconductive layers, while remains covering a second one of the semiconductive layers; selectively removing the first one of the semiconductive layers through the first opening to form a second opening; forming a contact in the first and second openings.