Backside Power Contact Structure Without SASI Process Complexity

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Solution Overview

Problem

The fabrication of integrated circuit devices with a backside power distribution network structure is hindered by the difficulty in controlling critical process parameters, particularly the height of the self-aligned substrate isolation layer, which is challenging due to process variations and narrow pitch requirements, leading to potential damage to the source/drain region.

Innovation Solution

The formation of a preformed placeholder in the substrate before front-side device processes, which is later replaced with a conductor to form a backside contact, eliminating the need for a self-aligned substrate isolation layer and simplifying the fabrication process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a self-aligned substrate isolation layer is used to protect the nano-sheet and increase process margin, then the nano-sheet protection is improved, but the manufacturing complexity and difficulty of controlling critical process parameters increase

Engineering Contradiction:
Improvenano-sheet protectionVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent removes the self-aligned substrate isolation layer from the fabrication process, extracting the problematic element that caused manufacturing complexity while maintaining nano-sheet protection through alternative means (direct substrate contact with controlled epitaxial growth)

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The placeholder is formed in advance during substrate preparation, before front-side device processing begins. This preliminary action allows the placeholder to be in place during critical processes without adding complexity to those processes, and enables subsequent replacement with the backside contact

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If a self-aligned substrate isolation layer is used to increase process margin, then the process margin is improved, but the manufacturing precision requirements for critical process parameters increase

Engineering Contradiction:
Improveprocess marginVSAvoidcritical process parameter control
Core Design Contradiction:
Manufacturing precisionVSMeasurement precision

Solution Approach 1:

The placeholder is designed as a temporary, disposable structure that is formed easily, serves its protective and alignment function during fabrication, and is then completely removed and replaced. This allows using a simple, easily manufacturable structure rather than requiring precise control of a permanent isolation layer

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Ease of manufacture

If a preformed placeholder is used without an SASI layer, then the fabrication complexity is reduced, but the source/drain region may be damaged due to process variations

Engineering Contradiction:
Improvefabrication simplicityVSAvoidsource/drain region protection
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The placeholder is formed with dimensions and positioning that provide a buffer or cushion against process variations. Its extended structure and strategic placement create margins that protect the source/drain region from damage even when process parameters vary, while still allowing simple fabrication without the SASI layer

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS20250324731A1Integrated circuit devices including a backside power distribution network structure and methods of forming the same
Publication Date: 2025.10.16 SAMSUNG ELECTRONICS CO LTD
  • US20250324731A1 patent drawing
  • US20250324731A1 patent drawing
  • US20250324731A1 patent drawing

AI summary

A method of forming an IC device includes: forming a sacrificial element in an epitaxial layer, the sacrificial element including a first portion and a second portion contacting the first portion; forming a transistor including a channel structure and a source/drain region on an upper surface of the epitaxial layer, wherein a portion of the epitaxial layer is between an upper surface of the second portion of the sacrificial element and the source/drain region; removing at least a portion of the epitaxial layer extending around the sacrificial element to expose a lower surface and sidewalls of the sacrificial element; forming an interlayer insulating layer surrounding the sacrificial element; replacing the sacrificial element with a power contact, the source/drain region contacting an upper surface of the power contact; and forming a power rail on a lower surface of the interlayer insulating layer that contacts a lower surface of the power contact.