Backside Power Delivery Circuit Edits Using Maskless Deep-Via Lithography
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Solution Overview
Problem
Current lithographic processing technologies are inefficient for inline circuit edits, requiring weeks to months for mask fabrication and production time, and are limited by the need for new masks for each design change, which hampers the semiconductor industry's ability to quickly adapt and improve feature scaling.
Innovation Solution
Implementing maskless e-beam lithography for inline circuit edits, allowing for real-time adjustments and edits to existing patterns without interrupting production, using a staggered beam aperture array to enhance throughput and precision, and combining with conventional optical lithography for complementary patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional optical lithography with mask fabrication is used for circuit edits, then manufacturing precision is maintained, but production time increases significantly (weeks to months)
Solution Approach 1:
The patent replaces the mechanical mask fabrication system with an electron beam direct-writing system. Instead of physically creating masks through multiple fabrication steps, the e-beam lithography tool directly writes the circuit patterns onto the wafer surface, eliminating the mask fabrication time while maintaining pattern precision through controlled electron beam exposure.
Solution Approach 2:
The patent uses digital circuit design data to directly generate the exposure pattern for e-beam writing, creating a digital copy of the desired circuit layout. This digital-to-physical direct translation eliminates the need for physical mask copies and their associated fabrication time, while preserving the original design precision.
2Adaptability or versatility
If new masks are fabricated for each design change, then circuit design adaptability is achieved, but device complexity and production time increase
Solution Approach 1:
The patent implements a dynamic, reconfigurable patterning system using e-beam lithography where the exposure pattern can be changed electronically without physical mask changes. The system accepts digital circuit design inputs and dynamically adjusts the electron beam writing pattern in real-time, enabling rapid adaptation to design changes without the complexity of mask re-fabrication.
Solution Approach 2:
The e-beam lithography system serves multiple functions: it can write different circuit patterns, modify existing patterns, and accommodate various design changes all through a single tool and process. This universal capability replaces the need for multiple specialized masks, reducing device complexity while maintaining design adaptability.
3Reliability
If traditional lithography processes are used, then manufacturing reliability is maintained, but productivity decreases due to sequential processing steps
Solution Approach 1:
The patent implements continuous e-beam writing across the wafer surface without interruption for mask changes. The electron beam continuously exposes the photoresist layer according to the digital circuit pattern, eliminating the downtime associated with mask fabrication and changeover, thereby maintaining manufacturing reliability while significantly improving productivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces production time by weeks, enables rapid prototyping and error correction, and allows for parallel testing of multiple solutions on a single wafer, improving the efficiency and speed of semiconductor manufacturing.
Implementation Method 1
accessing a backside of a front-end-fabricated conductive feedthrough structure using a maskless lithography process
Data Source
AI summary
Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a device layer including a plurality of transistor structures. A front-end routing layer is above the device layer, the front-end routing layer coupled to one or more of the plurality of transistors. A backside metal structure is below the device layer. A conductive feedthrough structure is directly coupling the backside metal structure to the front-end routing layer.