Backside Power Distribution Through Device Stratum
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Solution Overview
Problem
The challenge in semiconductor devices is to integrate high-performance and low-capacitance, low-power components within a single chip while optimizing power distribution, as traditional methods face issues with voltage drop and resistance in power interconnects.
Innovation Solution
The solution involves routing power lines from the backside of the integrated circuit through the device stratum to the device side, using larger area conductive contacts or vias to reduce resistance and improve power distribution, enabling efficient connection of transistors and logic circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power lines are routed through the device stratum using traditional methods, then the chip can be manufactured with standard processes, but voltage drop and resistance increase reduce power distribution efficiency
Solution Approach 1:
The patent routes power lines through the thickness dimension of the device stratum rather than only along the surface planes. By utilizing vertical pathways through the substrate, power distribution occurs in a third dimension, reducing the horizontal current path length and associated resistive losses while maintaining compatibility with standard manufacturing processes
Solution Approach 2:
The invention implements different conductive structures at different locations within the device stratum. High-conductivity materials and optimized cross-sectional areas are placed specifically in regions with highest current density requirements, while standard interconnects are used in lower-demand areas, thereby reducing overall power distribution losses without requiring uniform enhancement throughout the entire chip
2Loss of energy
If larger area conductive contacts or vias are used to reduce resistance, then power distribution efficiency improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The power distribution network is divided into multiple segments with conductive contacts distributed at various locations through the device stratum. Rather than requiring a single large-area contact, the system uses multiple smaller contacts that collectively provide low resistance pathways, reducing the complexity of forming any single contact while achieving the same overall effect
Solution Approach 2:
The patent implements nested conductive structures where smaller conductive elements are positioned within or alongside larger vias and contacts. This nested arrangement allows current to flow through multiple concentric pathways, effectively reducing resistance without requiring any single contact to be excessively large or complex to manufacture
3Reliability
If more power distribution pathways are created through the substrate, then voltage drop is reduced, but the chip area and manufacturing process complexity increase
Solution Approach 1:
The patent utilizes the vertical dimension of the substrate to create multiple power distribution pathways by forming conductive vias at different depths and locations through the thickness of the device stratum. This three-dimensional approach allows numerous parallel current paths without increasing the planar chip footprint, as the additional pathways are stacked vertically rather than spread horizontally
Solution Approach 2:
The power distribution system is segmented into multiple discrete conductive pathways distributed throughout the substrate volume. Each segment provides an independent current path, and their collective effect reduces voltage drop without requiring any single pathway to occupy excessive chip area, as the segments are distributed in three-dimensional space rather than concentrated on the surface
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances power distribution efficiency, reducing resistance and voltage drop, thereby enabling the integration of high-performance and low-power components within a single chip, addressing the limitations of traditional methods.
Implementation Method 1
a contact coupled to the supply line and routed through the device stratum and coupled to at least one of the plurality of transistor devices on the first side
Data Source
AI summary
An apparatus including a circuit structure including a device stratum; and a contact coupled to a supply line and routed through the device stratum and coupled to at least one device on a first side. A method including providing a supply from a package substrate to at least one transistor in a device stratum of a circuit structure; and distributing the supply to the at least one transistor using a supply line on an underside of the device stratum and contacting the at least one transistor on a device side by routing a contact from the supply line through the device stratum. A system including a package substrate, and a die including at least one supply line disposed on an underside of a device stratum and routed through the device stratum and coupled to at least one of a plurality of transistor devices on the device side.