Semiconductor Contact Layout with Backside Power and Drain Routing
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Solution Overview
Problem
The increasing complexity and power dissipation in semiconductor integrated circuits due to smaller geometries and denser metal lines lead to inefficient processing power and reduced performance, particularly in Vdd and Vss power routing, impacting cell scaling and RC delay.
Innovation Solution
A metal line routing method is implemented where common drain contacts are moved from the front-side to the back-side of the wafer, reducing lateral overlap with gate structures and improving capacitance, thereby enhancing functional density and operational speed by minimizing metal tracks in the same chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If common drain contacts are kept on the front-side with gate structures, then manufacturing process is simpler, but lateral overlap increases causing higher capacitance and slower processing speed
Solution Approach 1:
The patent moves common drain contacts from the front-side to the back-side of the wafer, utilizing the third dimension (depth/layer) to resolve the lateral overlap problem. This dimensional transition eliminates capacitance issues between contacts and gate structures while maintaining manufacturing feasibility through back-side processing techniques
2Power
If more metal lines are used for power routing, then power delivery capability improves, but RC delay increases reducing performance
Solution Approach 1:
The patent utilizes the back-side of the wafer to route power lines, creating vertical separation between power routing paths and logic circuits. This dimensional separation reduces parasitic capacitance and RC delay while maintaining adequate power delivery capability to the cells
3Productivity
If cell density is increased, then functional density improves, but power dissipation increases
Solution Approach 1:
The patent separates power routing to the back-side, allowing front-side cells to be densely packed without proportionally increasing power dissipation. The vertical separation reduces capacitive coupling and associated dynamic power consumption, enabling higher functional density with controlled power dissipation
Data Source
AI summary
A method includes: forming a plurality of first nanostructures arranged in a vertical direction; forming a gate strip surrounding each of the first nanostructures; growing a plurality of first epitaxial structures on either side of each of the first nanostructures; forming a first contact on a top end of a first one of the first epitaxial structures; and forming a second contact on a bottom end of the first one of the first epitaxial structures.