Backside Power Network and Capacitors for Dense FET Layouts

Solution Overview

Problem

Traditional semiconductor chip power delivery from the frontside leads to real estate allocation for power lines and significant power loss, limiting performance and logic density.

Innovation Solution

Implementing a backside power distribution network with embedded capacitors for power delivery and analog applications, utilizing hybrid bonding to connect frontside BEOL structures with backside power distribution networks in stacked FETs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If power is delivered from the frontside of the chip through multiple layers of wiring, then power can be delivered to the transistor, but valuable real estate on the chip is consumed and significant power is lost

Engineering Contradiction:

Improvepower lossVSAvoidreal estate on chip

Core Design Contradiction:

Loss of energyVSArea of stationary object

Solution Approach 1:

The patent inverts the traditional frontside power delivery approach by implementing power delivery from the backside of the chip. The backside power distribution network routes power through fewer layers directly to the transistor, reducing both the area occupied by power lines and the power loss during transmission. This inversion of the power delivery direction resolves the contradiction between minimizing real estate usage and minimizing power loss.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent utilizes the third dimension (vertical stacking) by implementing a backside power distribution network that accesses power from the opposite side of the chip. This dimensional change allows power to be delivered through a different path with fewer interconnect layers, reducing both the horizontal real estate requirements and the vertical power loss, thereby resolving the technical contradiction.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Loss of energy

If power is delivered from the frontside of the chip through multiple layers of wiring, then power can be delivered to the transistor, but significant power is lost during transmission

Engineering Contradiction:

Improvepower lossVSAvoidmultiple layers of wiring

Core Design Contradiction:

Loss of energyVSDevice complexity

Solution Approach 1:

The patent inverts the traditional frontside power delivery approach by implementing power delivery from the backside of the chip. The backside power distribution network routes power through fewer layers directly to the transistor, reducing both the area occupied by power lines and the power loss during transmission. This inversion of the power delivery direction resolves the contradiction between minimizing real estate usage and minimizing power loss.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent extracts the power delivery function from the frontside BEOL structure and implements it separately on the backside of the chip. By separating the power delivery path from the signal routing path and delivering power from the backside, the system reduces the number of wiring layers required and minimizes power loss, resolving the contradiction between device complexity and power loss.

Inventive Principle:

Principle #2Taking out (Extraction)

3Productivity

If frontside BEOL structure is hybrid bonded with backside power distribution network in stacked FETs, then logic density is increased and power performance is improved, but device structure becomes more complex

Engineering Contradiction:

Improvelogic densityVSAvoiddevice structure

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the FET device into stacked components with separate frontside BEOL structures and backside power distribution networks. Each segment can be optimized independently, and the hybrid bonding interface connects them efficiently. This segmentation enables increased logic density through vertical stacking while managing structural complexity through modular design and standardized bonding interfaces.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS20250372504A1FET with backside power distribution network and capacitor

Publication Date: 2025.12.04 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A semiconductor device is provided that includes a non-stacked field effect transistor (FET) or a stacked FET with at least one capacitor and a backside power distribution network. The at least one capacitor is configured for power delivery, analog applications or when two capacitors are present one of the capacitors is configured for power delivery and the other capacitor is configured for analog applications.