Backside Power Delivery Layout for Fine-Pattern Semiconductor Regions
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Solution Overview
Problem
The increasing demand for high-performance, high-speed, and multifunctional semiconductor devices requires improved integration and electrical properties, particularly in the development of backside power delivery networks (BSPDN) where existing structures face challenges in efficiently integrating fine patterns and maintaining effective power delivery.
Innovation Solution
A semiconductor device design featuring a substrate with multiple active regions, device isolation layers, gate structures, source/drain regions, conductive through-structures, and power delivery structures that allow for enhanced integration and electrical connectivity, including frontside and backside interconnection structures, to support varied pattern densities and efficient power distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fine patterns are implemented to increase integration, then degree of integration is improved, but manufacturing precision requirements worsen
Solution Approach 1:
The patent introduces a vertical dimension by implementing a backside power delivery network (BSPDN) with conductive through-structures extending through the substrate thickness. This allows power delivery paths to be established in the vertical dimension rather than only in the planar dimension, enabling fine pattern implementation on the front surface without compromising power delivery capability.
Solution Approach 2:
The substrate is segmented into functionally distinct regions: front surface active regions for device operation and back surface power delivery regions for power distribution. This segmentation allows independent optimization of each region, enabling fine patterns on the front surface while maintaining robust power delivery on the back surface.
2Use of energy by moving object
If backside power delivery network is implemented, then power delivery efficiency is improved, but device complexity increases
Solution Approach 1:
The patent inverts the conventional power delivery approach by placing power delivery structures on the back surface of the substrate rather than on the front surface. This inversion allows power delivery networks to be implemented without interfering with the active device regions, improving power delivery efficiency while maintaining relatively simple device structures.
3Reliability
If conductive through-structures are added for BSPDN, then electrical connectivity is improved, but manufacturing complexity increases
Solution Approach 1:
The conductive through-structures are formed as part of the substrate fabrication process before the active device regions are fully constructed. This preliminary action allows the power delivery pathways to be pre-established through the substrate, simplifying subsequent manufacturing steps and improving overall electrical connectivity without significantly increasing manufacturing complexity.
Data Source
AI summary
A semiconductor device may include a substrate including a first active region including first active patterns spaced apart by a first interval, a second active region including second active patterns spaced apart by a second interval, first and second source/drain regions on the first and second active regions, first and second contact structures connected to the first and second source/drain regions, first and second conductive through-structures connected to the first and second contact structures, a power delivery structure in contact with bottom surfaces of the first and second conductive through-structures, a frontside interconnection structure, and a backside interconnection structure. The first conductive through-structure may be connected to the first source/drain region through the first contact structure. The second conductive through-structure may be connected to the second source/drain region through the frontside interconnection structure. The second interval may be different than the first interval.