Backside Power Structure Alignment in 3D FinFET Semiconductor Devices
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Solution Overview
Problem
As demands for high performance, high speed, and multifunctionality in semiconductor devices increase, there is a need for improved reliability and integration, particularly in semiconductor devices with backside power delivery networks and three-dimensional FinFET structures, which face challenges in operating characteristics due to decreased planar metal oxide semiconductor FET sizes.
Innovation Solution
A semiconductor device design featuring a substrate with active regions, gate structures, source/drain regions, a vertical power structure, backside insulating layers, and alignment insulating layers, where the vertical power structure extends through the substrate and is connected to a backside power structure via an opening in the alignment insulating layer, enhancing electrical connectivity and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the planar metal oxide semiconductor FET size is decreased to increase integration density, then the degree of integration is improved, but the operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar 2D FET structures to three-dimensional FinFET structures with vertical channels. This dimensional change allows the channel to extend vertically into the substrate, increasing the effective channel area without increasing the planar footprint, thereby maintaining integration density while improving operating characteristics through better current drive and control.
Solution Approach 2:
The FinFET structure embeds the channel vertically within the substrate, nesting the active region inside the wafer volume rather than spreading it horizontally. This nesting approach allows multiple FinFET devices to be packed closely in the planar direction while each device utilizes vertical space for its channel, achieving high integration without sacrificing individual device performance.
2Power
If a backside power delivery network is implemented to improve power distribution, then the power delivery capability is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent inverts the conventional power delivery approach by placing power rails and power distribution structures on the backside of the wafer instead of the front side. This inversion allows power delivery networks to be formed independently of the active device regions, simplifying the manufacturing process by separating power distribution fabrication from transistor fabrication steps while still achieving high power delivery capability.
3Productivity
If the vertical power structure width is minimized to increase integration density, then the degree of integration is improved, but the alignment precision requirements increase
Solution Approach 1:
The patent employs self-aligned fabrication processes where the vertical power structures are automatically positioned relative to the FinFET devices through conformal deposition and etching steps. The power structures are formed using the device features themselves as alignment references, eliminating the need for separate high-precision alignment steps and thereby achieving narrow power structure widths without increasing alignment precision requirements.
Data Source
AI summary
A semiconductor device comprising: a substrate including an active region extending in a first direction; a gate structure extending in a second direction on the active region; source/drain regions on the active region and adjacent the gate structure; a backside insulating layer on a lower surface of the substrate; a vertical power structure between adjacent source/drain regions, wherein the vertical power structure extends through the substrate and the backside insulating layer and has an exposed lower surface exposed; an interlayer insulating layer on the backside insulating layer; a backside power structure that extends through the interlayer insulating layer and is connected to the vertical power structure; and a first alignment insulating layer between the backside insulating layer and the interlayer insulating layer, wherein the first alignment insulating layer has a first opening exposing the lower surface of the vertical power structure and contacts the backside power structure.