Backside Power Network Layout for Stacked-Channel FinFETs
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Solution Overview
Problem
The increasing demand for high-performance semiconductor devices with high integration and multi-functionality poses challenges in overcoming the limitations of planar metal oxide semiconductor FETs, particularly in terms of operating characteristics due to size reduction, which necessitates the development of advanced structures like FinFETs with three-dimensional channels and backside power delivery networks.
Innovation Solution
A semiconductor device design featuring active regions with stepped structures, gate structures, channel layers, source/drain regions, sidewall spacer layers, and backside contact plugs, along with a backside power delivery network, enhances the reliability and functionality of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar MOSFET structure is used, then manufacturing process is simple, but operating characteristics deteriorate due to size reduction
Solution Approach 1:
The patent transitions from planar (2D) MOSFET structure to three-dimensional FinFET structure with vertical fins extending from the substrate. This dimensional change provides increased gate control over the channel while maintaining scaled device dimensions, thereby improving operating characteristics without sacrificing manufacturability.
Solution Approach 2:
The FinFET structure embeds multiple channel layers within a compact footprint, with fins nested vertically. The gate structure wraps around the channel in a multi-layer configuration, providing enhanced control volume within a reduced planar area, thus maintaining performance while enabling further scaling.
2Productivity
If device integration is increased, then device functionality improves, but power delivery becomes insufficient
Solution Approach 1:
The patent introduces a backside power delivery network that utilizes the substrate's rear surface and vertical dimension to route power and ground signals. Power rails are formed on the backside of the substrate, connecting to source/drain regions through contact holes, thereby delivering power to high-density integrated circuits without occupying front-side real estate.
Solution Approach 2:
The power delivery system is segmented into dedicated power rails and ground rails formed on the backside substrate, with separate contact hole structures for power and signal routing. This segmentation allows independent optimization of power delivery paths from the front-side circuit design, ensuring stable power supply to highly integrated devices.
3Reliability
If channel layers are spaced apart in vertical direction, then gate control is improved, but device footprint increases
Solution Approach 1:
The patent positions channel layers in the vertical dimension (third direction perpendicular to substrate surface) rather than spreading them laterally. Multiple channel layers are stacked vertically with spacing in the vertical direction, allowing enhanced gate control through wrap-around gate structures while maintaining a compact planar footprint.
Solution Approach 2:
Multiple channel layers are merged into a single vertical FinFET structure, with the gate structure wrapping around all channel layers simultaneously. This merging of multiple channels into a compact vertical arrangement provides cumulative gate control effectiveness while occupying minimal planar area, effectively combining multiple transistor channels in one footprint.
Data Source
AI summary
A semiconductor device includes: active regions extending in a first direction on a substrate; a device isolation layer; gate structures intersecting the active regions and extending in a second direction; a plurality of channel layers on the active regions spaced apart from each other in a third direction and surrounded by the gate structures; first and second source/drain regions spaced apart from each other, the source/drain regions being connected to the plurality of channel layers and in recess regions on both sides of the gate structures; sidewall spacer layers on side surfaces of the source/drain regions; and a backside contact plug penetrating one of the active regions, and contacting a lower surface of the first source/drain region, wherein the active regions include a step region, and wherein the first active region extends onto side surfaces of at least an upper region of the backside contact plug in the second direction.