Backside Power Delivery With Frontside Rails for Tap-Cell-Free Layouts
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Solution Overview
Problem
The integration of power delivery networks in semiconductor chip architectures is challenged by increasing device densities, leading to inefficiencies in space usage and interruptions in circuit row designs due to the need for tap cells in backside power delivery architectures.
Innovation Solution
The method involves forming a semiconductor device with a front side including a metal wire M2 and multiple power rails, and a back side with a metal wire M1 and a power delivery network, using through-silicon vias to connect the power rails from the back side to the front side, allowing for wider power rails and reduced resistance, thereby eliminating the need for tap cells and optimizing space usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power delivery network layers are moved to the back side of the chip, then power delivery efficiency is improved, but tap cells are required which interrupt circuit row designs and reduce space utilization
Solution Approach 1:
The patent moves the power delivery network from the traditional planar front-side layout to a three-dimensional configuration where power rails are formed on the back side of the semiconductor substrate, connected to front-side circuitry through vertical through-silicon vias. This dimensional transition eliminates the need for tap cells that interrupt circuit rows, as power can be delivered vertically through the substrate rather than requiring lateral connections within the circuit plane.
Solution Approach 2:
Instead of bringing power delivery connections up to the front side where circuit rows are formed, the patent inverts the approach by forming power rails on the back side and delivering power downward through the substrate. This inversion eliminates the need for front-side tap cells and their associated design interruptions, allowing continuous circuit row layouts.
2Loss of energy
If wider power rails are used to reduce resistance, then power delivery efficiency is improved, but more fabrication steps are required
Solution Approach 1:
The patent combines the formation of wide power rails with the existing through-silicon via fabrication process. The same via formation, filling, and planarization steps that create TSVs are utilized to create the wide power rail connections, eliminating the need for separate wide-rail fabrication processes and reducing overall manufacturing complexity.
Solution Approach 2:
The through-silicon via fabrication process serves multiple functions: it creates the vertical interconnects for signal transmission and simultaneously forms the wide power rail connections. This multi-functionality reduces the total number of fabrication steps required, as the same process infrastructure and tooling are used for both signal and power delivery network formation.
Data Source
AI summary
A method for forming a semiconductor device includes forming a front side of the semiconductor device, the front side comprising a metal wire M2, and a plurality of power rails coupled to the M2. Further, the method includes forming a through silicon via (TSV) from a back side of the semiconductor device to the front side, the TSV connecting a first power rail of the front side with a metal wire M1 on the back side. Further, the method includes forming a power delivery network on the back side, the TSV providing power from the power delivery network to the front side.