Backside Power Network With Frontside TSVs for Lower 3D IC IR Drop
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Solution Overview
Problem
Three-dimensional integrated circuits (3D ICs) experience increased IR drops due to electrical resistances in power grid structures, leading to higher power consumption and degraded device performance as more layers are stacked, which limits the efficiency of power delivery and occupies valuable routing space for signal lines.
Innovation Solution
Implementing a backside power distribution network and frontside deep through silicon vias (TSVs) to reduce IR drops by directly transmitting power from the power source to embedded devices, while also increasing routing space for signal lines within the interlayer dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more layers are stacked in 3D ICs, then chip density is increased, but IR drops increase leading to higher power consumption
Solution Approach 1:
The patent transitions from traditional two-dimensional power distribution to a three-dimensional architecture by implementing through-silicon vias (TSVs) that extend vertically through the substrate. This allows power to be distributed from both frontside and backside of the chip, creating a volumetric power network that reduces current path length and resistance, thereby lowering power consumption while maintaining high chip density
2Quantity of substance
If more layers are stacked in 3D ICs, then chip density is increased, but device performance degrades due to increased IR drops
Solution Approach 1:
The power distribution network is segmented into multiple independent pathways by implementing both frontside and backside power grids connected through TSVs. This segmentation creates parallel current paths that reduce overall resistance and minimize IR drops, ensuring stable power delivery to each stacked layer and maintaining device performance despite increased integration density
3Area of stationary object
If traditional power grid structures are used, then routing space is occupied, but power delivery efficiency is reduced
Solution Approach 1:
The patent utilizes the vertical dimension by implementing through-silicon vias and backside power distribution, effectively moving power routing from a planar constraint to a three-dimensional space. This allows power to be delivered through the thickness of the chip rather than only laterally, freeing up lateral routing space while improving power delivery efficiency through shorter and multiple current paths
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively decreases IR drops by up to 5% and enhances power delivery efficiency, allowing for improved performance and reduced power consumption in 3D ICs by utilizing a backside power distribution network and frontside deep TSVs to distribute power with less resistance.
Implementation Method 1
Implementing a backside power distribution network and frontside deep through silicon vias (TSVs) to reduce IR drops by directly transmitting power from the power source to embedded devices
Data Source
AI summary
The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.