Backside Power Network With Integrated Gate Signal Routing
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Solution Overview
Problem
Current semiconductor device architectures face challenges in scaling due to increasing resistance in power delivery interconnects as devices shrink, particularly in providing effective power connections to transistor gates through backside power delivery methods.
Innovation Solution
A backside power distribution network is designed with integrated signal lines and power rails, where n-channel and p-channel field-effect transistors on a wafer have power rails connected to source/drain regions on the backside and signal lines connected to the gates, enabling efficient power delivery and signal transmission between adjacent transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If device dimensions are scaled down, then device size is reduced, but resistance of interconnects increases exponentially
Solution Approach 1:
The patent moves the power delivery network from the frontside to the backside of the wafer, utilizing the third dimension (vertical stacking) to resolve the resistance issue. By routing power delivery layers to the backside, the invention creates shorter and more direct power paths to transistor gates, bypassing the resistance bottleneck caused by scaled-down frontside interconnects.
2Reliability
If backside power delivery is implemented, then power delivery resistance is reduced, but gate connection capability is lacking
Solution Approach 1:
The backside of the wafer is designed to accommodate multiple functions: power delivery through power rails and gate signaling through signal lines. This multi-functional approach allows the backside power delivery network to simultaneously provide both power and control signals to transistors, making the architecture versatile enough to replace traditional frontside interconnects for both purposes.
3Adaptability or versatility
If signal lines and power rails are integrated on backside, then device functionality is improved, but fabrication complexity increases
Solution Approach 1:
The backside power delivery network is segmented into distinct functional components: power rails for power delivery and signal lines for gate control. This segmentation allows each component to be optimized independently for its specific function while simplifying the fabrication process, as different material stacks and processing conditions can be applied to different regions of the backside.
Data Source
AI summary
A backside power distribution network is provided having an integrated signal line with a backside connection to a transistor gate. In one aspect, a semiconductor device includes: NFETs and PFETs adjacent to one another on a frontside of a wafer; power rails, connected to source/drain regions of the NFETs and PFETs, present on a backside of the wafer in a space between adjacent NFETs and in a space between adjacent PFETs; and a signal line, connected to a gate of the NFETs and PFETs, present on the backside of the wafer in a space between an adjacent NFET and PFET. The NFETs and PFETs can each include a stack of active layers, and gates surrounding at least a portion of each of the active layers in a gate-all-around configuration. A method of fabricating the present semiconductor devices is provided.