Backside Power Gating Layout for Silicon Area and Loss Reduction

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Solution Overview

Problem

Voltage regulation (VR) circuits on modern integrated circuit (IC) chips consume significant silicon area, increasing costs and reducing the available space for logic circuitry due to the use of transistors for power gating.

Innovation Solution

Implementing backside power gating using thin-film transistors on the backside layers of ICs, replacing traditional frontside VR circuits, which are formed with materials like two-dimensional semiconductor films and metal oxide films, to save silicon area and improve efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional frontside voltage regulation circuits using transistors are used, then power gating function is achieved, but silicon area is significantly consumed

Engineering Contradiction:
Improvepower gating functionVSAvoidsilicon area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent moves the power gating transistor from the frontside to the backside of the semiconductor substrate, utilizing the third dimension (depth/layer) to resolve the area conflict. The transistor is formed in a trench etched into the backside of the substrate, allowing it to occupy vertical space rather than horizontal silicon area, thus enabling power gating functionality without consuming valuable frontside circuit area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Power

If traditional frontside voltage regulation circuits are used, then power control is achieved, but resistance is high and power loss increases

Engineering Contradiction:
Improvepower control capabilityVSAvoidpower loss
Core Design Contradiction:
PowerVSLoss of energy

Solution Approach 1:

By positioning the transistor in the backside trench, the source and drain regions can be directly connected to power and ground pads through vertical vias, creating shorter current paths. This three-dimensional configuration reduces the resistive losses compared to planar frontside layouts where current must travel through longer interconnect paths.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent creates a simplified version of the voltage regulation function by using a single transistor in the backside trench that directly switches power to the load, eliminating the need for complex frontside voltage regulation circuitry while achieving the essential power control function with lower resistance.

Inventive Principle:
Principle #26Copying

3Reliability

If more silicon area is allocated to voltage regulation circuits, then power gating performance improves, but available area for logic circuitry decreases

Engineering Contradiction:
Improvevoltage regulation performanceVSAvoidlogic circuitry density
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The invention relocates the voltage regulation transistor to the backside of the substrate in a trench structure, effectively moving it out of the two-dimensional plane occupied by logic circuitry. This allows the transistor to be formed in the vertical dimension without encroaching on the horizontal space needed for high-density logic circuit design, thereby maximizing both power gating performance and logic circuit capacity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250112122A1Backside power gating
Publication Date: 2025.04.03 INTEL CORP
  • US20250112122A1 patent drawing
  • US20250112122A1 patent drawing
  • US20250112122A1 patent drawing

AI summary

Integrated circuit (IC) devices and systems with backside power gates, and methods of forming the same, are disclosed herein. In one embodiment, an integrated circuit die includes a device layer with one or more transistors, a first interconnect over the device layer, a second interconnect under the device layer, and one or more power gates under the device layer.