Backside Power Gating Transistor for IC Area Reduction
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Solution Overview
Problem
Existing integrated circuit (IC) designs face challenges with power consumption due to static leakage, as header and footer transistors required for power gating need to be large to minimize resistance and leakage, leading to area and speed issues, and achieving a high Ion/Ioff ratio is difficult when integrated in the front end of line.
Innovation Solution
The integration of a field effect transistor on the backside of the semiconductor substrate, connected through TSV connections to the power delivery network, allowing for power management and higher Ion/Ioff ratios, thus acting as a header or footer transistor without the area and speed limitations of front-end transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If header and footer transistors are integrated in the front end of line, then they can control power supply to IC blocks, but they consume significant area and degrade IC speed due to large size requirements
Solution Approach 1:
The patent moves the power gating transistors from the traditional front-end planar location to the backside of the substrate, utilizing the third dimension (vertical space) to resolve the area conflict. This allows the transistors to be positioned where they do not compete with the active logic circuit area while still performing their power control function through TSV connections.
Solution Approach 2:
Instead of placing power gating transistors in the conventional front-end location, the patent inverts the approach by integrating them on the backside of the substrate. This inversion allows the transistors to be larger without impacting the front-end logic area, as they are now positioned in the opposite spatial location.
2Power
If header and footer transistors are made large to reduce resistance, then power delivery is improved, but IC speed is degraded
Solution Approach 1:
By relocating the transistors to the backside, the patent enables larger transistor sizes that provide lower resistance and better power delivery without the speed penalty that would occur if similarly large transistors were placed in the front-end path of the logic circuit.
Solution Approach 2:
The patent introduces TSV (Through-Silicon Via) connections as an intermediary element that couples the backside power gating transistors to the front-end logic blocks. This intermediary allows the large transistors to deliver power efficiently while the TSVs provide the necessary electrical connection without requiring the transistors to be in the direct signal path.
3Area of moving object
If header and footer transistors are made small to reduce area, then area consumption is reduced, but resistance increases and leakage control becomes difficult
Solution Approach 1:
The backside positioning allows the transistors to achieve larger effective areas for better leakage control and lower resistance without consuming front-end logic area. The vertical relocation decouples the area requirement from the logic circuit density constraint.
Solution Approach 2:
The patent changes the physical location parameter of the transistors from front-end to backside, which fundamentally alters the area-leakage-resistance trade-off. This parameter change enables the transistors to be optimized for power control performance without being constrained by the area budgets of the logic blocks.
4Reliability
If high Ion/Ioff ratio is achieved in front-end transistors, then power gating effectiveness is improved, but transistor size and complexity increase
Solution Approach 1:
The patent extracts the power gating transistor function from the front-end logic blocks and places it on the backside. This separation allows the power gating transistors to be independently optimized for high Ion/Ioff ratios using specialized structures without increasing the complexity of the front-end logic transistor design.
Solution Approach 2:
The patent applies different design optimizations to different locations: the front-end logic blocks maintain their standard design, while the backside power gating transistors are specially designed with structures optimized for high Ion/Ioff ratios. This local quality differentiation allows each region to be optimized for its specific function without compromising the other.
Data Source
AI summary
An integrated circuit (IC) chip that includes a semiconductor substrate including active devices on its front side, and at least part of a power delivery network (PDN) on its back side, is disclosed. In one aspect, the PDN includes a power supply terminal (Vdd) and a reference terminal (Vss) at the back of the IC. A plurality of TSV (Through Semiconductor Via) connections through the substrate bring the power to the front of the substrate. A field effect transistor is integrated at the back side of the substrate, and includes a source electrode, a drain electrode, and a gate electrode, which are contacted at the back side of the substrate. The IC further includes a gate control terminal for controlling the gate voltage. The transistor is coupled between the power supply terminal and one or more of the active devices of the IC.