Backside Power Grid for Analog Cell Boundary Noise

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Solution Overview

Problem

In integrated circuit (IC) manufacturing, the increasing density of transistors and reduced component sizes lead to challenges in managing noise interference between digital and analog circuits, particularly due to the formation of parasitic bipolar junction transistors, which cause latchup and affect the operation of adjacent analog circuits.

Innovation Solution

The introduction of a backside power grid in the analog-cell-boundary regions, which repurposes otherwise empty space to accommodate power grid segments, reducing frontside routing congestion and facilitating the routing of conductive segments, thereby mitigating noise interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If transistor density is increased and component sizes are reduced, then productivity and integration level are improved, but noise interference between digital and analog circuits increases

Engineering Contradiction:
Improvetransistor densityVSAvoidnoise interference
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent introduces a backside power grid that extends from the frontside through via structures into the substrate, utilizing the vertical dimension and backside surface to route power connections. This three-dimensional power distribution approach allows power grid segments to be positioned in multiple layers and locations, reducing frontside routing congestion and minimizing noise coupling between digital and analog circuits while maintaining high transistor density

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Object-affected harmful factors

If guard ring structures are added to reduce noise interference, then noise protection is improved, but device complexity and manufacturing steps increase

Engineering Contradiction:
Improvenoise interferenceVSAvoidstructure complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The backside power grid serves multiple functions simultaneously: it provides power distribution to high-density transistors, acts as an electrostatic discharge (ESD) protection structure, and functions as a noise shielding mechanism. By integrating these protective functions into the existing power grid infrastructure rather than adding separate guard ring structures, the patent reduces overall device complexity while maintaining noise protection capabilities

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The power grid segments themselves provide noise protection and ESD protection functions without requiring separate dedicated protective structures. The via structures and substrate connections that are necessary for power distribution also serve as noise shielding pathways and ESD protection mechanisms, allowing the power grid to protect itself and adjacent circuits

Inventive Principle:
Principle #25Self-service

3Use of energy by moving object

If power grid segments are routed on the frontside, then power distribution is achieved, but routing congestion increases and analog circuit operation is affected

Engineering Contradiction:
Improvepower distributionVSAvoidanalog circuit operation
Core Design Contradiction:
Use of energy by moving objectVSEase of operation

Solution Approach 1:

The patent routes power grid segments through the substrate from the frontside to the backside, utilizing the vertical dimension and backside surface for power distribution. This allows power connections to be made without occupying frontside routing space, reducing congestion and minimizing interference with analog circuit signals while ensuring stable power delivery to high-density transistor regions

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20240014136A1Analog-cells-boundary region with buried power grid segment, semiconductor device including same and method of manufacturing same
Publication Date: 2024.01.11 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240014136A1 patent drawing
  • US20240014136A1 patent drawing
  • US20240014136A1 patent drawing

AI summary

A semiconductor device includes: first and second active regions (ARs) included correspondingly in abutting first and second analog cell regions, a region where the first and second analog cell regions abut (analog-cell-boundary (ACB) region) extending from about a top boundary of the first AR to about a bottom boundary of the second AR; via-to-PGBM_1st-segment contact structures (VBs) correspondingly being under the first or second ARs, a long axis of each VB and a short axis of each of the first and second ARs having about a same length; and a PG segment in a first buried metallization layer (PGBM_1st segment) under the VBs, the PGBM_1st segment underlapping a majority of each of the VBs, and a Y-midline of the PGBM_1st segment being at or proximal to where the first and second analog cell regions abut and thus being at or proximal to a middle of the ACB region.