Backside Power Grid Rails for Compact IC Routing and TDDB Risk
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Solution Overview
Problem
As semiconductor devices shrink in size, the increased risk of dielectric breakdowns, such as time-dependent dielectric breakdowns (TDDB), occurs due to reduced distances between conductive paths, which can lead to voltage breakdowns and affect the reliability of integrated circuits.
Innovation Solution
The implementation of self-aligned via structures and conductive rail networks within dielectric regions allows for electrical connections between gate, source, and drain regions without conventional metal layers, reducing the real estate needed for integrated circuits and minimizing dielectric breakdown risks by aligning metal wires and vias accurately.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional metal layers and routing structures are used to connect gate, source, and drain regions, then electrical connections can be established, but the area required for integrated circuits increases and the risk of dielectric breakdowns increases due to reduced distances between conductive paths
Solution Approach 1:
The patent introduces conductive rails extending in a first direction and metal wires extending in a second direction (different from the first direction) to create three-dimensional routing paths. This dimensional approach allows electrical connections without requiring short horizontal distances between conductive paths, thereby reducing dielectric breakdown risk while maintaining compact area usage.
Solution Approach 2:
The patent uses conductive rails as intermediary structures that extend from the front side through the substrate to the back side, where they connect to backside power grids. These rails serve as mediators that eliminate the need for conventional metal layers and vias on the front side, reducing both area requirements and dielectric breakdown risks.
2Area of stationary object
If self-aligned via structures and conductive rail networks are implemented, then the area required for integrated circuits is reduced and routing resources are saved, but the manufacturing process complexity increases
Solution Approach 1:
The patent forms conductive rails and their alignment structures (such as spacer layers and etch masks) in advance before final metal wire deposition. This preliminary action establishes precise alignment pathways that simplify subsequent manufacturing steps, reducing overall process complexity despite the introduction of new structures.
Solution Approach 2:
The patent implements nested structures where spacer layers are formed around conductive rails, and etch masks are formed around spacers, creating concentric alignment features. This nesting approach allows multiple alignment functions to be achieved within a single manufacturing sequence, reducing process complexity.
Data Source
AI summary
A semiconductor device includes a substrate, a dielectric region, a first fin structure, a second fin structure, a plurality of conductive regions, a first conductive rail and a conductive structure. The dielectric region is situated on the substrate. The first fin structure protrudes from the substrate and the dielectric region. The second fin structure protrudes from the substrate and the dielectric region, and extends parallel to the first fin structure. The conductive regions are situated on the dielectric region. The first conductive rail is situated within the dielectric region, and electrically connected to a first conductive region of the plurality of conductive regions. Opposite sides of the first conductive rail face the first fin structure and the second fin structure, respectively. The conductive structure penetrates through the substrate and formed under the first conductive rail, and is electrically connected to the first conductive rail.