Backside Power Grid Layout for 3D Die Stacking Voltage Droop
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Solution Overview
Problem
Efficient routing of power signals across semiconductor dies is limited by the consumption of on-die area by through silicon vias and keep out zones, leading to increased voltage droop and redesign challenges, which affect both portable and high-performance computing devices.
Innovation Solution
Implementing backside metal layers with specific power routing configurations, including L-shaped and rectangular routes, to reduce resistivity and voltage droop, and enhance charge sharing across vertically stacked semiconductor dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Extent of automation
If through silicon vias and keep out zones are used for interconnects between stacked dies, then vertical communication between dies is enabled, but on-die area is consumed which limits area for active devices and signal routes
Solution Approach 1:
The patent routes power signals through the vertical dimension by utilizing backside metal layers of stacked dies. Instead of consuming additional horizontal on-die area, the solution creates power delivery networks in the vertical stack, allowing power signals to traverse between dies through interconnect structures without occupying precious planar area on any single die.
2Ease of operation
If power signals are routed through numerous metal layers to reach nodes on semiconductor chips, then connectivity is achieved, but resistive voltage droop increases due to increased resistance
Solution Approach 1:
The patent segments the power delivery network into multiple backside metal layers, each serving specific power routing functions. By dividing the power distribution into hierarchical levels (different metal layers for different routing distances and current requirements), the solution reduces the resistance of individual trace segments while maintaining overall connectivity, thereby reducing IR droop.
Solution Approach 2:
The patent implements local quality by creating thick, low-resistance power traces in backside metal layers specifically where high current delivery is needed, while other metal layers can use thinner traces for signal routing. This localized optimization of trace geometry and material properties reduces voltage droop in critical power delivery paths without affecting other functions.
3Productivity
If the area for routing power signals is reduced to accommodate more nodes and signals, then device functionality increases, but the distance between power contacts increases which widens the floorplan
Solution Approach 1:
The patent resolves the floorplan expansion issue by moving power routing from the horizontal plane to the vertical dimension. Power contacts and distribution networks are established in backside metal layers of stacked dies, allowing power delivery without increasing the lateral footprint of the device. This enables high-density integration while maintaining compact package dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces power routing resistivity, minimizes voltage droop, and improves thermal dissipation, allowing for efficient power delivery and reduced redesign time in semiconductor chip designs.
Implementation Method 1
forms multiple backside metal layers vertically adjacent to a backside of a silicon substrate of the second semiconductor die
Data Source
AI summary
An apparatus and method for efficiently routing power signals across semiconductor dies. A semiconductor fabrication process (or process) places a first semiconductor die in an integrated circuit and stacks a second semiconductor die vertically adjacent to the first semiconductor die. The process forms multiple backside metal layers vertically adjacent to a backside of a silicon substrate of the second semiconductor die. The process forms a first backside metal layer that includes at least a first power route that forms a rectangle within the first backside metal layer. The process forms a second backside metal layer that includes at least a second power rail that forms an L-shape within the second backside metal layer. The process connects one or more corners of the rectangle of the first power rail to a corresponding corner of a separate power rail of the second backside metal layer that forms an L-shape.