Backside Power Delivery Layout for Lower-Resistance IC Cells
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits faces challenges due to variability in conventional fabrication processes, limiting further reduction to the 10 nanometer node, and existing power delivery methods occupy valuable space, complicating signal routing and increasing resistance.
Innovation Solution
Implementing backside power delivery through boundary-aligned contact-vias (BACVs) that connect transistors to a power network from the wafer backside, reducing power network resistance and enabling efficient cell placement without interference with signal routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling multi-gate transistors, then existing manufacturing infrastructure can be maintained, but manufacturing precision deteriorates at 10 nanometer node and below
Solution Approach 1:
The patent inverts the conventional power delivery approach by delivering power from the backside of the substrate rather than the front side. This inversion allows power networks to be formed on the backside where they do not interfere with frontside transistor fabrication processes, thereby maintaining manufacturing precision at 10nm node while reducing process variability through separated fabrication streams
2Power
If power delivery networks are implemented on the front side, then power can be delivered to transistors, but valuable space is occupied and signal routing is complicated
Solution Approach 1:
The patent moves the power delivery network from the two-dimensional front side plane to the third dimension by utilizing the backside of the substrate. This dimensional transition separates power routing from signal routing in space, eliminating interference and reducing routing complexity while maintaining efficient power delivery to transistors through vertical vias
3Productivity
If transistor density is increased on the chip, then circuit capacity is improved, but power network resistance increases
Solution Approach 1:
The patent segments the power delivery system into separate frontside and backside networks. The backside power network is specifically optimized for high-current power delivery with dedicated power vias and lower resistance paths, while the frontside handles signaling. This segmentation allows high transistor density on the frontside without compromising power delivery efficiency
Data Source
AI summary
Integrated circuit structures having backside power delivery are described. In an example, an integrated circuit structure includes a device layer within a cell boundary, the device layer having a front side and a backside, and the device layer including a source or drain structure. A source or drain trench contact structure is on the front side of the device layer. The source or drain trench contact structure is coupled to the source or drain structure. A metal layer is on the backside of the device layer. A via structure couples the metal layer to the source or drain trench contact structure. The via structure is overlapping and parallel with a cell row boundary of the cell boundary.