Backside Power IC Inspection Using Bitline Lock-In Thermography
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Solution Overview
Problem
Conventional defect detection techniques for integrated circuits (ICs) with backside power delivery architectures face limitations due to opaque metal layers, resulting in low spatial resolution and restricted access, particularly with optical fault isolation and lock-in thermography methods.
Innovation Solution
A defect detection apparatus utilizing lock-in thermography with high spatial resolution, achieved by modulating bitlines in SRAM cells to generate thermal emissions and capturing images with a thermal imaging sensor, allowing for precise identification of defects down to 200 nanometers, even through metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional optical fault isolation techniques are used on ICs with backside power delivery, then the inspection process is simple, but the spatial resolution is low and defects cannot be detected through opaque metal layers
Solution Approach 1:
The patent replaces conventional optical inspection methods with lock-in thermography, which uses thermal imaging to detect defects. This substitution enables detection through opaque metal layers by measuring thermal emissions from defective regions, achieving single-bit resolution imaging capability while maintaining a manageable inspection process
Solution Approach 2:
The patent changes the detection parameter from optical reflection to thermal emission measurement. By monitoring temperature variations and thermal patterns in the IC, the system can detect defects with high spatial resolution even through backside power delivery metal layers, resolving the contradiction between measurement precision and device complexity
2Measurement precision
If lock-in thermography is used to detect defects through metal layers, then spatial resolution improves, but the inspection method becomes more complex and time-consuming
Solution Approach 1:
The patent applies preliminary thermal imaging to locate defective regions before physical delayering is performed. By using lock-in thermography to identify defect locations in advance, the system reduces the time required for subsequent delayering and analysis processes, as technicians can focus only on identified problem areas rather than examining the entire IC structure
Solution Approach 2:
The patent introduces thermal imaging as an intermediary detection method between conventional optical inspection and physical delayering. This intermediary step provides high-precision defect localization without requiring immediate physical intervention, thereby reducing overall inspection time while maintaining high measurement precision
3Manufacturing precision
If backside power delivery architecture is used, then transistor density increases, but optical access to transistor layers is blocked by metal stacks
Solution Approach 1:
The patent substitutes optical detection methods with thermal detection methods to overcome the blocking effect of metal stacks in backside power delivery architectures. Thermal emissions can penetrate or be detected through the metal layers, enabling defect detection in high-density transistor arrangements without compromising optical access
Solution Approach 2:
The patent transitions from two-dimensional optical surface inspection to three-dimensional thermal field measurement. By detecting thermal emissions that propagate through multiple layers, the system can locate defects in high-density transistor configurations even when direct optical access is blocked by the backside power delivery metal stacks
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables precise defect detection with single-bit resolution imaging, significantly improving the ability to pinpoint defects in ICs with backside power delivery architectures, reducing delayering time and enhancing physical failure analysis efficiency.
Implementation Method 1
modulating bitlines in SRAM cells to generate thermal emissions and capturing images with a thermal imaging sensor
Implementation Method 2
A defect detection apparatus utilizing lock-in thermography with high spatial resolution
Data Source
AI summary
Systems, apparatus, articles of manufacture, and methods are disclosed to improve inspection techniques for integrated circuits with backside power delivery. An example disclosed apparatus includes at least one programmable circuit to at least one of instantiate or execute the machine readable instructions to modulate first and second bitlines for a bitcell in a memory array of an integrated circuit between first and second voltages at a frequency for a period of time, the modulating of the first and second bitlines to produce a periodic heat signal in the integrated circuit, cause a thermal imaging sensor to capture a series of images of the integrated circuit during the period of time, and determine a location of a defect in the integrated circuit based on the series of images.