Backside Power Feedthroughs for Maskless Inline Circuit Edits
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Solution Overview
Problem
Current lithographic processing technologies are inefficient for inline circuit edits, requiring the fabrication of new masks for each edit iteration, which prolongs production time and limits flexibility in making design changes across a wafer and field.
Innovation Solution
Implementing maskless e-beam lithography for inline circuit editing, allowing for edits to be made without interrupting production flow by creating access points to transistors and routing backside power delivery, thereby reducing the need for new masks and enabling faster prototyping and debug cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional lithographic processing is used for inline circuit edits, then new masks must be fabricated for each edit iteration, but this prolongs production time and reduces flexibility
Solution Approach 1:
The patent extracts the lithography step from the mask-dependent process chain by implementing maskless lithography. This allows circuit edits to be performed directly on the wafer without requiring new mask fabrication, thereby eliminating the time-consuming mask production step while maintaining design change flexibility
Solution Approach 2:
The patent performs preliminary actions by pre-defining access points to transistors and routing structures during the initial fabrication process. These pre-established access points enable subsequent inline circuit edits to be performed quickly without requiring new masks, thus reducing production time while maintaining adaptability
2Adaptability or versatility
If new masks are fabricated for each edit iteration, then design changes can be made, but this increases manufacturing complexity and cost
Solution Approach 1:
The patent removes the mask fabrication step from the circuit edit process by implementing maskless lithography. This eliminates the complexity and cost associated with mask manufacturing while preserving the ability to make design changes through direct wafer processing
Solution Approach 2:
The patent uses digital design data to directly pattern the wafer through maskless lithography, replacing the physical mask copy process. This digital-to-wafer direct translation eliminates the need for physical mask fabrication and reduces manufacturing complexity
3Productivity
If conventional lithography is used for circuit edits, then production flow must be interrupted, but this reduces productivity
Solution Approach 1:
The patent performs preliminary actions by pre-defining access points and routing structures during initial fabrication. This allows subsequent circuit edits to be performed as quick overlay processes without interrupting the main production flow, thereby maintaining high productivity
Solution Approach 2:
The patent enables continuous production flow by performing circuit edits as overlay processes that do not require stopping the fabrication line. The maskless lithography approach allows edits to be integrated into the existing production sequence, maintaining continuous useful action
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces turnaround time for logic repair and debug, allows for parallel testing of multiple solutions on a single wafer, and eliminates the need for dedicated whitespace, thereby enhancing productivity and reducing production time by weeks compared to conventional methods.
Implementation Method 1
forming a conductive feedthrough structure using a maskless lithography process
Data Source
AI summary
Lithographic methodologies involving, and apparatuses suitable for, inline circuit edits are described. In an example, an integrated circuit structure includes a device layer including a plurality of transistor structures. A front-end routing layer is above the device layer, the front-end routing layer coupled to one or more of the plurality of transistors. A backside metal structure is below the device layer. A conductive feedthrough structure is directly coupling the backside metal structure to the front-end routing layer. The conductive feedthrough structure is a monolithic structure extending through the device layer.