Backside Power Interconnect for Low-Voltage-Drop Semiconductor Fabrication
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Solution Overview
Problem
Semiconductor devices face challenges in achieving high reliability and performance due to increasing complexity and integration, particularly in reducing voltage drop in power delivery networks as line widths are reduced.
Innovation Solution
The semiconductor device incorporates a backside interconnection structure on the substrate's lower surface for power delivery, with a dummy mold structure on the frontside interconnection structure to enhance power performance and reduce voltage drop, and a method involving a carrier substrate and bonding layers to facilitate fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If line widths are reduced to achieve miniaturization, then device integration increases, but voltage drop in power delivery networks worsens
Solution Approach 1:
The patent introduces a backside interconnection structure that delivers power from the rear surface of the substrate, adding a third dimension (vertical/z-axis) to the power delivery network. This allows power lines to be positioned closer to active elements in the vertical direction while maintaining larger lateral dimensions, thereby reducing voltage drop despite reduced line widths for miniaturization
2Loss of energy
If backside interconnection structure is added to reduce voltage drop, then power performance improves, but device complexity increases
Solution Approach 1:
The interconnection network is segmented into frontside and backside components. The backside interconnection structure handles power delivery functions separately from signal routing on the frontside, allowing each subsystem to be optimized independently and simplifying the overall design despite the added complexity
3Reliability
If dummy mold structure is added to maintain structural integrity, then fabrication reliability improves, but manufacturing complexity increases
Solution Approach 1:
The dummy mold structure is formed as a preliminary element during the fabrication process, establishing mechanical support and defining interconnection patterns before subsequent processing steps. This preliminary action prevents structural collapse during thinning and bonding operations, ensuring fabrication reliability while using standard semiconductor manufacturing techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves power performance and reliability by reducing voltage drop and maintaining structural integrity during fabrication, addressing the limitations of conventional frontside interconnection structures.
Implementation Method 1
bonding the semiconductor substrate to the carrier substrate by disposing the first bonding layer and the second bonding layer to face each other
Data Source
AI summary
A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate including a frontside on which an active pattern is formed and a backside opposite the frontside, an electronic element on an active region in which the active pattern is formed, a frontside interconnection structure, in which a power line connected to the electronic element is disposed, on the frontside of the substrate, a backside interconnection structure, which includes a backside line connected to the electronic element, on the backside of the substrate, a through via connecting the power line with the backside line by passing through the substrate, and a dummy mold structure on the frontside interconnection structure, having a first cross-sectional thickness greater than a second cross-sectional thickness of the frontside interconnection structure.