Backside Power Rail Interposer for Dense Semiconductor Packaging
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in miniaturization and interconnection, requiring further improvements to advance the state of the art, particularly in devices with complex and dense semiconductor packages that demand tighter voltage regulation and isolation between analog and digital circuits.
Innovation Solution
The integration of a gate-all-around (GAA) field-effect-transistor (FET) structure with a backside power rail and an interposer, which includes metallization layers for power supply and signal lines, allows for die-to-die connections, simplifying fabrication processes and reducing packaging costs while enabling miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If modern packaging technologies (POP, FO) are used to drive miniaturization and interconnection, then device density and intercommunication improve, but manufacturing complexity and cost increase
Solution Approach 1:
The patent combines multiple semiconductor dies with different functions (analog die, digital die, RF die) into a single integrated package substrate, merging what would traditionally be separate packages into one unified structure. This achieves high device density while managing complexity through integrated design rather than multiple discrete components.
Solution Approach 2:
The patent utilizes three-dimensional stacking and vertical interconnection through through-silicon vias (TSVs) to achieve high density in the vertical dimension rather than only lateral expansion. This allows multiple dies to be stacked and interconnected vertically, dramatically increasing device density without proportionally increasing package footprint or manufacturing complexity.
2Productivity
If complex and dense semiconductor packages are designed to increase thermal density, then device performance improves, but voltage regulation and circuit isolation become more difficult
Solution Approach 1:
The patent segments the package into functionally isolated zones: analog circuitry, digital circuitry, and RF circuitry are physically separated on different dies and locations within the package. This segmentation allows independent voltage regulation and power management for each functional domain, maintaining reliability despite high overall package density and thermal load.
Solution Approach 2:
The patent introduces dedicated power management integrated circuits (PMICs) and voltage regulator modules as intermediary components between the power supply and various circuit blocks. These intermediaries provide isolated voltage regulation for analog, digital, and RF sections, preventing voltage fluctuations and noise from one section from affecting others, thus maintaining reliability in high-density packages.
Data Source
AI summary
A semiconductor device includes: a first chip including a plurality of first device features and a plurality of first interconnect structures disposed above the first device features; a second chip including a plurality of second device features and a plurality of second interconnect structures disposed above the second device features; and an interposer bonded to the first chip and the second chip, and disposed opposite the first and second device features from the first and second interconnect structures; wherein the interposer includes a plurality of power rails configured to deliver power to the first and second chips.