Backside Power Isolation Module with Sacrificial Cap Etch Flow

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Solution Overview

Problem

In backside power delivery applications, replacing the silicon substrate with a dielectric material is necessary to prevent shorting between adjacent contacts, but removing silicon selectively is extremely difficult, especially when using silicon germanium as a placeholder, which hinders the development of improved semiconductor devices.

Innovation Solution

A method involving recessing a sacrificial layer relative to a silicon layer, isotropically etching, depositing a cap layer, and forming backside contact metallization in a semiconductor device with a superlattice structure on a shallow trench isolation, allowing for the replacement of silicon with a dielectric material without affecting the sacrificial layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If silicon substrate is replaced with dielectric material in backside power delivery application, then shorting between adjacent contacts is prevented, but selective removal of silicon becomes extremely difficult

Engineering Contradiction:
Improveprevention of shorting between contactsVSAvoiddifficulty of selective silicon removal
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

A sacrificial layer is introduced as an intermediary material between the silicon substrate and the final dielectric structure. This sacrificial layer can be selectively removed to expose the silicon substrate for controlled etching, while the silicon itself remains protected until the final stage of the process

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The sacrificial layer is deposited and patterned in advance before the final dielectric material is formed. This preliminary action creates a temporary structure that guides the subsequent silicon removal process, enabling precise control over where and how silicon is removed without affecting surrounding areas

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If silicon layer is completely removed to form opening, then backside contact metallization can be formed, but structural support and alignment reference are lost

Engineering Contradiction:
Improveformation of backside contactVSAvoidloss of structural support
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

Instead of completely removing the silicon layer, the process performs partial removal to the extent needed to expose the sacrificial layer and form the opening for metallization. The silicon layer is etched just enough to reach the sacrificial layer level, maintaining structural support while enabling the required electrical connections

Inventive Principle:
Principle #16Partial or excessive action

3Quantity of substance

If feature sizes are shrunk to achieve greater circuit density, then circuit density increases, but electrostatic coupling and parasitic effects worsen

Engineering Contradiction:
Improvecircuit densityVSAvoidelectrostatic coupling and parasitic capacitance
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The superlattice structure introduces local variations in material composition and properties at the nanoscale. By creating alternating layers with different electrical characteristics, the structure enhances electrostatic coupling locally while managing parasitic effects through the tailored band structure of the superlattice

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the formation of semiconductor devices with improved electrostatic coupling and reduced parasitic capacitance and off-state leakage, addressing the challenges of silicon removal and enhancing device performance.

Implementation Method 1

recessing a sacrificial layer relative to a silicon layer of a substrate to form a recessed region

Methodology Applied
Scientific EffectSelective etching:

Implementation Method 2

isotropically etching the silicon layer to form a first opening

Methodology Applied
Scientific EffectIsotropic etching:

Implementation Method 3

depositing a cap layer in the first opening

Methodology Applied
Scientific EffectMaterial deposition: Deposition (physical)

Implementation Method 4

oxidizing the remaining silicon layer to form an oxidized silicon layer

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 5

depositing a flowable layer on the in the second opening on the oxidized silicon layer

Methodology Applied
Scientific EffectMaterial deposition: Deposition (physical)

Data Source

PatentUS20240379438A1Isolation module formation for backside power delivery application
Publication Date: 2024.11.14 APPLIED MATERIALS INC
  • US20240379438A1 patent drawing
  • US20240379438A1 patent drawing
  • US20240379438A1 patent drawing

AI summary

Semiconductor devices and methods of manufacturing the same are described. The method includes combining selective recess of a sacrificial layer and isotropic etching of a silicon layer in order to form a protective cap that will allow the silicon layer of the substrate to be etched without affecting the sacrificial layer.