Backside Power Isolation Module for Tight Contact Patterning
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Solution Overview
Problem
Backside power delivery in semiconductor devices poses challenges in patterning electrical contact features isolated from each other within tight spaces without impacting the performance of transistors on the front side of the chip.
Innovation Solution
A method involving selective deposition, angled etching, selective removal plasma etching, recess filling, and inter-layer dielectric formation to create a metal contact embedded within an inter-layer dielectric on the backside of a chip, while protecting extension regions on the front side.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If backside power delivery is implemented to eliminate front-side power tracks and enable optimal metal layer fabrication, then power delivery efficiency and manufacturing flexibility are improved, but patterning electrical contact features in tight spaces becomes more difficult and transistor performance may be impacted
Solution Approach 1:
The patent segments the contact formation process into multiple distinct stages: forming contact holes through the substrate, depositing isolation modules in the gaps between contacts, and completing the interconnect structure. This segmentation allows each feature (contacts and isolation modules) to be patterned and processed independently, reducing the complexity of patterning tightly spaced electrical contact features on the backside while maintaining power delivery efficiency.
2Adaptability or versatility
If electrical contact features are patterned in tight spaces on the backside, then backside power delivery is enabled, but transistor performance on the front side may be impacted
Solution Approach 1:
The patent introduces isolation modules as intermediary dielectric structures positioned in the gaps between electrical contact features on the backside. These isolation modules act as mediators that provide electrical isolation and mechanical support, enabling the patterning of contact features in tight spaces while preventing any negative impact on front-side transistor performance through proper grounding and isolation.
3Manufacturing precision
If multiple processing steps are performed to form isolation modules and metal contacts, then manufacturing precision is improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions by first forming the contact holes through the substrate and establishing the contact features before depositing the isolation modules in the gaps. This preliminary action allows subsequent processing steps to focus on isolation and interconnect formation with higher precision, as the contact feature locations are already established. The multi-step approach breaks down complex manufacturing into manageable stages, improving overall precision while maintaining ease of manufacture through systematic processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of a metal contact on the backside of a chip without compromising the front-side transistor performance, facilitating efficient backside power delivery.
Implementation Method 1
performing a selective deposition process to form selective cap layers at bottoms of contact trenches
Implementation Method 2
performing a substrate angled etch process to etch sidewalls of the contact trenches
Implementation Method 3
performing a substrate selective removal plasma (SRP) etch process to isotropically etch the substrate within the contact trenches
Implementation Method 4
performing a recess fill process to fill the contact trenches with dielectric layers
Implementation Method 5
performing a substrate isotropic etch process to partially remove the substrate within the ILD recess
Data Source
AI summary
A method of forming a portion of a gate-all-around field-effect transistor includes performing a selective deposition process to form selective cap layers at bottoms of contact trenches formed within portions of a substrate isolated by shallow trench isolations (STIs), wherein the contact trenches each interface with an S/D epitaxial (epi) layer with an extension region, performing a substrate angled etch process to etch sidewalls of the contact trenches, enlarging top critical dimension (CD) of the contact trenches, performing a substrate selective removal plasma (SRP) etch process to isotropically etch the substrate within the contact trenches, performing a recess fill process to fill the contact trenches with dielectric layers, performing an inter-layer dielectric (ILD) recess process to partially remove the substrate between the dielectric layers within the contact trenches and form an ILD recess, and performing a substrate isotropic etch process to partially remove the substrate within the ILD recess.