Backside Power Delivery Layout for Low-IR-Drop Semiconductor Devices
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Solution Overview
Problem
Conventional semiconductor devices face challenges in minimizing routing congestion and reducing the area size due to the conventional power delivery network configuration, which results in increased current-resistance (IR) drop and potential performance deterioration.
Innovation Solution
The semiconductor device features a power delivery network layer on one surface and signal wiring on the opposite surface, with through-vias connecting these layers to reduce area size and improve reliability, while an insulating layer and semiconductor layer are strategically stacked to separate logic and passive elements, minimizing interference and enhancing insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the power delivery network layer and signal wiring are disposed on the same surface of the wafer, then the routing is simpler, but the area size increases and routing congestion occurs
Solution Approach 1:
The patent applies dimensionality change by moving the power delivery network layer from the first surface to the second surface of the wafer, creating a three-dimensional layered structure. This separates power routing from signal routing in the vertical dimension, reducing area size and routing congestion on each surface while maintaining routing simplicity through systematic layer design.
2Area of stationary object
If the power delivery network layer is moved to the second surface of the wafer, then the area size is reduced and routing congestion is minimized, but the manufacturing process becomes more complex
Solution Approach 1:
The patent segments the wafer into two distinct surfaces with dedicated functions: the first surface for signal wiring and logic elements, and the second surface for the power delivery network layer. This segmentation allows independent optimization of each layer's manufacturing process while reducing overall area size and routing congestion.
3Area of stationary object
If logic elements and passive elements are disposed close to each other, then the area size is reduced, but interference increases and insulation is compromised
Solution Approach 1:
The patent uses vertical stacking to separate logic elements and passive elements into different depth levels within the substrate layer. This three-dimensional arrangement reduces lateral distance and area size while maintaining adequate insulation through vertical separation and embedded insulating structures.
Data Source
AI summary
A semiconductor device and a method for manufacturing the same is provided. The semiconductor device includes a power delivery network layer; an insulating layer on the power delivery network layer and having an opening therein; a semiconductor layer filling the opening and covering the insulating layer; a first through-via extending through the semiconductor layer and electrically connected to the power delivery network layer; a second through-via extending through the insulating layer and the semiconductor layer and electrically connected to the power delivery network layer; a logic element on the semiconductor layer and electrically connected to the first through-via; and a passive element on the semiconductor layer and electrically connected to the second through-via.