Backside Power Delivery Layout for Low-Voltage-Drop Semiconductors
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Solution Overview
Problem
As semiconductor devices become more highly integrated, the reduced widths of wiring patterns and via patterns lead to increased voltage drops in power delivery networks, affecting the reliability and performance of these devices.
Innovation Solution
The semiconductor device incorporates a substrate with a first and second active pattern, a gate structure, source/drain patterns, and back source/drain contacts, with a power line connected to the back source/drain contacts on the bottom surface of the substrate, where the power line has a width smaller than the distance between the back source/drain contacts to reduce voltage drop.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wiring patterns and via patterns are reduced in width to achieve higher integration, then device integration is improved, but voltage drops in power delivery networks increase
Solution Approach 1:
The patent introduces a third dimension by forming back source/drain contacts that extend vertically through the substrate from the rear surface. This vertical dimension provides additional power delivery pathways that are independent of the lateral wiring patterns, thereby reducing voltage drops without compromising integration density in the planar dimensions.
Solution Approach 2:
The power delivery network is segmented into multiple independent pathways: front-side wiring patterns for signal routing and back-side contacts for power delivery. This segmentation allows each pathway to be optimized for its specific function, with the back contacts providing dedicated low-resistance power paths that compensate for the reduced width of front-side wiring.
2Area of moving object
If back source/drain contacts are positioned close together to minimize area, then device area is reduced, but routing crosstalk between contacts increases
Solution Approach 1:
By moving the power delivery contacts to the rear surface of the substrate and extending them vertically, the patent separates the power delivery function from the signal routing plane. This spatial separation in the vertical dimension reduces electromagnetic coupling and crosstalk between adjacent contacts while maintaining compact lateral dimensions.
Solution Approach 2:
The substrate itself acts as an intermediary that electrically isolates and spatially separates the back source/drain contacts. The substrate material provides natural shielding and spacing that reduces crosstalk between adjacent contacts while allowing them to be positioned in a compact arrangement.
3Loss of energy
If power lines are made wider to reduce voltage drop, then voltage delivery is improved, but device area and routing complexity increase
Solution Approach 1:
The patent utilizes the vertical dimension by forming back contacts that extend through the substrate thickness. This provides additional cross-sectional area for current flow in the vertical direction, effectively reducing resistance and voltage drops without requiring wider lateral power lines that would increase device area.
Solution Approach 2:
The back source/drain contacts provide localized low-resistance power delivery paths directly at the active transistor regions. This concentrated local quality of high conductivity where needed eliminates the need for wide distributed power lines across the entire device area.
Data Source
AI summary
A semiconductor device includes a backside power delivery network (BSPDN). The semiconductor device includes a substrate, a first active pattern extending in a first direction, on a top surface of the substrate, a second active pattern extending in the first direction, and spaced apart from the first active pattern in a second direction intersecting the first direction, on the top surface of the substrate, a gate structure extending in the second direction, on the first active pattern and the second active pattern, a first source/drain pattern connected to the first active pattern, on a side surface of the gate structure, a second source/drain pattern connected to the second active pattern, on the side surface of the gate structure, back source/drain contacts penetrating the substrate, and a first power line connected to the back source/drain contacts on a bottom surface of the substrate.