Backside Power Delivery Channels for Stacked Memory Logic Heat Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor systems face issues of high thermal concentration and degradation at logic chips due to direct power delivery, leading to increased latency and potential defects from defective logic chips, which affect the reliability and yield of the semiconductor system.
Innovation Solution
Implementing logic chips stacked above memory chips with a dielectric silicon layer and conductive channels for backside power delivery, which distributes thermal energy more evenly and allows for pre-testing of logic chips to ensure their functionality before integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If power is delivered directly to logic chips, then power delivery is simple, but thermal concentration increases and reliability decreases
Solution Approach 1:
The patent introduces an intermediary power delivery structure consisting of a substrate with multiple power delivery paths between the power source and logic chips. This intermediary structure distributes power through multiple routes, preventing thermal concentration and improving reliability without requiring complex external cooling systems. The substrate acts as a mediator that transforms the simple but problematic direct power delivery into a distributed, thermally-managed power distribution network.
2Productivity
If logic chips are stacked above memory chips, then integration density improves, but thermal concentration at logic chips increases
Solution Approach 1:
The patent segments the power delivery function into multiple independent power delivery paths on the substrate. Each path provides power to logic chips through different routes, distributing the thermal load across multiple channels rather than concentrating it at a single location. This segmentation allows high-density stacking while maintaining acceptable thermal conditions through parallel power distribution channels.
3Productivity
If defective logic chips are used, then manufacturing yield improves, but system reliability decreases
Solution Approach 1:
The patent changes the parameter of power delivery from a single concentrated path to multiple distributed paths with different characteristics. This parameter change enables the system to tolerate defects in individual paths or chips, as alternative paths can compensate for failures. The multi-path architecture transforms the binary accept/reject criterion into a more nuanced system where defective chips can be bypassed, maintaining both yield and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces thermal concentration, improves latency, enhances reliability, and increases the yield of semiconductor systems by ensuring only functional logic chips are used, thereby extending the life of electronic devices and reducing electronic waste.
Implementation Method 1
distributes thermal energy more evenly
Data Source
AI summary
Methods, systems, and devices for backside power delivery to logic of a memory architecture are described. A semiconductor system may implement logic chips stacked above stacks of memory chips, where the stacks of memory chips are positioned above circuitry associated with providing power to the semiconductor system. The semiconductor system may include a dielectric layer above the logic chips including conductive channels. For example, the circuitry may deliver power to the logic chips based on transferring power along power delivery vias to the conductive channels which may provide the power to the logic chips. In some examples, a front side of the logic chips may be bonded with a backside of the stacks of memory chips, and a backside of the logic chips may be bonded with the conductive channels, such that power is delivered to the backside of the logic chips.