Backside Power Mesh Layout for Lower IR Drop in Semiconductor Power Delivery
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Solution Overview
Problem
Existing semiconductor devices face challenges in minimizing power consumption while maintaining high-speed operations, as many technologies require additional circuitry that increases chip area, and existing power mesh configurations on the front surface lead to higher resistance and IR drop.
Innovation Solution
The implementation of a backside power mesh for the local power line VVDD, which reduces resistance and IR drop by forming thicker metal lines and vias under the semiconductor substrate, allowing for more efficient power delivery without occupying routing area on the chip surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power mesh is formed on the front surface of the semiconductor substrate, then power delivery is achieved, but resistance and IR drop increase
Solution Approach 1:
The patent moves the power mesh from the traditional front surface (2D plane) to the back surface of the semiconductor substrate, utilizing the third dimension (depth/layer) to resolve the contradiction. By forming the power mesh on the back surface, the patent achieves low-resistance power delivery paths without interfering with front surface circuit routing, thereby reducing IR drop while maintaining reliable power supply.
Solution Approach 2:
The patent inverts the conventional approach by placing the power mesh on the back surface instead of the front surface of the semiconductor substrate. This inversion allows the power mesh to utilize thicker metal layers and longer vias for lower resistance, while avoiding the routing congestion and high resistance issues associated with front surface implementation.
2Use of energy by moving object
If additional circuitry is added to minimize power consumption, then power efficiency improves, but chip area increases
Solution Approach 1:
The back surface power mesh serves multiple functions simultaneously: it provides low-resistance power delivery paths, acts as a ground reference plane, and enables efficient decoupling capacitor placement. This multi-functionality achieves power consumption optimization without requiring separate dedicated structures, thereby avoiding additional chip area expansion.
Solution Approach 2:
The patent merges the power delivery function with the back surface structure, combining power mesh, ground planes, and decoupling capacitors into a unified back-side architecture. This integration achieves comprehensive power management functionality without proportionally increasing chip area, as these functions share the same physical space on the back surface.
3Loss of energy
If thicker metal lines and vias are used in power mesh, then resistance decreases, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions during the early stages of semiconductor fabrication by forming the back surface power mesh structure before final circuit patterning. The thick metal lines and vias are established in advance using standard backend-of-line (BEOL) processes, allowing subsequent finer circuit features to be patterned without compromising the power mesh structure. This sequencing reduces manufacturing complexity despite the use of thick conductors.
Data Source
AI summary
Semiconductor devices are provided. A semiconductor device includes a semiconductor substrate, a power switch, a first power mesh and a second power mesh. The power switch is formed over the front surface of the semiconductor substrate. The first power mesh is formed over the power switch and is directly connected to the first terminal of the power switch. The second power mesh is formed over the back surface of the semiconductor substrate and is directly connected to the second terminal of the power switch.