Backside Power Rail Layout for Mixed-Height Standard Cells
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Solution Overview
Problem
Fabricating integrated circuit (IC) wafers with mixed cell libraries of different heights, such as 6T and 9T cells, is challenging due to misalignment of signal lines and power rails, requiring irregular patterns that complicate the formation of a consistent density level.
Innovation Solution
Separating signal lines and power rails by forming them on opposite sides of the wafer, with signal lines in the BEOL region and power rails in the backside region, allowing for straight line patterns and accommodating different cell heights without irregular shapes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If signal lines and power rails are formed on the same side of the wafer to accommodate different cell heights, then alignment between adjacent cell regions can be achieved, but irregular patterns and shapes are required which complicate fabrication
Solution Approach 1:
The patent divides the wafer into two separate sides: the front side (BEOL region) contains signal lines with constant pitch, while the back side (backside region) contains power rails with varying pitch. This segmentation allows each side to be optimized independently - signal lines maintain simple straight patterns for easy fabrication, while power rails accommodate different cell heights through varying pitch on the backside, eliminating the need for irregular patterns on the front side.
Solution Approach 2:
The patent moves power rails from the front side (BEOL region) to the back side of the wafer, utilizing the third dimension (depth/thickness of the wafer) to resolve the conflict. By distributing power rails on the backside, the patent enables straight signal line patterns on the front side while still providing power distribution to cells of different heights through the vertical separation of signal and power pathways.
2Adaptability or versatility
If different cell heights are accommodated with varying power rail pitch, then different cell libraries can be integrated, but signal lines and power rails misalign in adjacent regions
Solution Approach 1:
The patent separates signal distribution and power distribution into different spatial locations - signal lines are confined to the front side BEOL region with uniform pitch, while power rails are located on the back side with varying pitch. This segmentation allows power rails to have different pitches in different regions to accommodate various cell heights without affecting the uniform signal line pattern, thus maintaining alignment while supporting cell library diversity.
Solution Approach 2:
The backside of the wafer acts as an intermediary layer that mediates between the uniform signal line requirements of the front side and the varying power distribution needs of different cell types. Power rails on the backside can be positioned with varying pitch to match different cell heights, while signal lines on the front side maintain constant pitch, with vertical connections (vias) serving as intermediaries to connect the two systems.
3Productivity
If straight line patterns are used for signal lines, then fabrication efficiency is improved, but power rails cannot accommodate different cell heights
Solution Approach 1:
The patent divides the interconnect function into two separate systems: signal lines on the front side with constant pitch that can be formed using simple straight line patterns for high fabrication efficiency, and power rails on the back side with varying pitch that can accommodate different cell heights. This segmentation allows each system to be optimized for its specific function without compromise.
Solution Approach 2:
The patent resolves the conflict between straight signal line patterns and varying power rail pitch by moving power rails to the back side of the wafer. This dimensional separation allows signal lines to maintain simple straight patterns on the front side for efficient fabrication, while power rails on the backside can have varying pitch configurations to accommodate different cell heights through the vertical depth of the wafer structure.
Data Source
AI summary
Embodiments of the invention provide a multi-layer integrated circuit (IC) structure that includes a back-end-of-line (BEOL) region at a first side of a wafer. A backside region is at a second side of the wafer that is opposite the first side of the wafer. A set of signal lines are in the BEOL region, and a set of power rails are in the backside region. The set of signal lines includes a substantially constant signal-line pitch between each signal line in the set of signal lines. The set of power rails includes a substantially varying power-rail pitch between each power rail in the set of power rails.