Semiconductor Package Backside Power Network for Dense Cell Layouts
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Solution Overview
Problem
The challenge in integrated circuit fabrication is to create more compact and densely packed devices with enhanced computing capabilities, where power and ground signals need to be efficiently provided to cells without obstructing further scaling due to crowded routing areas.
Innovation Solution
The implementation of buried power rails in integrated circuits, where power and ground signals are provided from the back side of the substrate, reducing the need for long signal paths through metallization layers and allowing for a more compact design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power rails are embedded in a stack of metallization layers over the devices, then power and ground signals can be provided to the cells, but the signal path becomes long and the routing areas become crowded
Solution Approach 1:
The patent moves the power distribution network from the traditional planar metallization layers above the devices to a three-dimensional structure where power rails are formed within trenches in the substrate. This dimensional change allows power signals to be delivered vertically and laterally through the substrate, bypassing the crowded routing areas and reducing signal path length while maintaining reliable power delivery to all cells.
2Reliability
If power rails are designed in already crowded routing areas of the cells, then power signals can be distributed, but further scaling of the cells is prevented
Solution Approach 1:
The patent segments the power distribution function from the signal routing function by creating dedicated power rails within substrate trenches. This segmentation allows power signals to be distributed through independent vertical and lateral paths in the substrate, freeing up the crowded routing areas for data signals and enabling continued cell scaling without compromising power distribution reliability.
3Reliability
If traditional metallization layer power rails are used, then power delivery is achieved, but the signal path length increases and cell density decreases
Solution Approach 1:
The patent implements power delivery through vertical trenches in the substrate rather than through horizontal metallization layers. This dimensional change creates shorter signal paths by delivering power directly to device contacts from below, reducing the area required per cell while maintaining reliable power delivery to all transistors in the integrated circuit.
Data Source
AI summary
A semiconductor package and a manufacturing method thereof is provided. The semiconductor package includes a first semiconductor die, including a substrate and transistors formed at a front side of the substrate; a power distribution network, spreading at a back side of the substrate and penetrating through the substrate, to provide power and ground signals to the transistors; a dielectric material, laterally surrounding the first semiconductor die; and a second semiconductor die, having a central portion bonded with the first semiconductor die and a peripheral portion in contact with the dielectric material.