Backside Power Delivery Network for Low-Resistance MOSFET Scaling
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Solution Overview
Problem
The scale-down of MOSFETs in integrated circuit devices leads to deterioration in operational properties and reliability issues, necessitating improved electrical characteristics and structural enhancements.
Innovation Solution
The integrated circuit device incorporates a power delivery network layer with a backside conductive structure penetrating the substrate to connect source/drain patterns to the power delivery network, and a lower insulating pattern below the source/drain patterns to prevent short circuits, enhancing electrical and reliability characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If MOSFETs are scaled down to meet increasing demand for small pattern size and reduced design rule, then device integration density is improved, but operational properties deteriorate and reliability issues arise
Solution Approach 1:
The patent transitions from planar MOSFET structures to vertically stacked three-dimensional structures. Multiple channel patterns are stacked in the vertical direction (third direction) to increase effective channel width without increasing lateral footprint. This dimensional transition allows continued scaling while maintaining operational properties through increased device area in the vertical dimension.
Solution Approach 2:
The patent implements nested structures where gate electrodes are positioned between stacked channel patterns, and insulating patterns are embedded within the substrate to provide electrical isolation. The backside conductive structures are nested within the substrate to connect to lower interconnection lines, creating a compact nested architecture that maximizes functionality within limited space.
2Productivity
If MOSFETs are scaled down, then integration density is improved, but contact resistance increases and electrical characteristics deteriorate
Solution Approach 1:
The patent introduces vertical stacking of channel patterns to increase effective channel width without increasing lateral dimensions. This allows higher integration density while maintaining electrical characteristics by providing multiple parallel conduction paths through the stacked structure, effectively increasing the total conductive area.
Solution Approach 2:
The patent divides the channel structure into multiple segmented patterns stacked vertically, with gate electrodes between them. This segmentation creates multiple independent conduction paths that can be controlled separately, improving electrical characteristics by distributing current flow across multiple segments rather than relying on a single scaled-down channel.
3Reliability
If backside conductive structures are added to penetrate the substrate and connect source/drain patterns to power delivery network, then electrical characteristics are improved, but device complexity increases
Solution Approach 1:
The patent utilizes the vertical dimension by penetrating the substrate with backside conductive structures to establish electrical connections between lower interconnection lines and source/drain patterns. This vertical connection approach improves electrical characteristics by providing direct low-resistance paths without adding lateral complexity to the planar layout.
Solution Approach 2:
The backside conductive structures serve multiple functions: they provide electrical connection to lower interconnection lines, act as part of the power delivery network, and enable vertical integration of multiple device layers. This multi-functionality reduces the need for separate dedicated structures, thereby managing complexity while improving electrical performance.
4Reliability
If lower insulating patterns are added below source/drain patterns to prevent short circuits, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent introduces lower insulating patterns as intermediary elements positioned between the source/drain patterns and the substrate. These insulating patterns act as mediators to prevent direct electrical contact (short circuits) between conductive elements while allowing the device structure to remain compact. The insulating patterns are strategically placed only where needed for isolation.
Solution Approach 2:
The lower insulating patterns are applied locally beneath specific source/drain patterns rather than uniformly across the entire device. This localized approach provides short circuit prevention exactly where electrical isolation is needed, while minimizing the addition of overall structural complexity in regions where isolation is not required.
Data Source
AI summary
An integrated circuit device includes: a substrate, a power delivery network layer including a lower interconnection line, on a bottom surface of the substrate, source/drain patterns including horizontally spaced-apart first and second patterns, on the substrate, a backside conductive structure that penetrates the substrate and electrically connects the first pattern to the power delivery network layer, and a lower insulating pattern extending below the second pattern, and in contact with a portion of the lower interconnection line.