Backside Power Delivery Package Layout for Logic Die Heat Dissipation
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Solution Overview
Problem
Existing semiconductor packages face challenges in heat dissipation and reliability, which affect their performance and durability.
Innovation Solution
A semiconductor package design that includes a logic die with a backside power delivery network layer, an interposer die with higher thermal conductivity, and a mold layer covering the interposer die and memory dies, along with a supporting substrate for enhanced heat dissipation and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If conventional semiconductor package structure is used, then manufacturing process is simple, but heat dissipation performance is insufficient
Solution Approach 1:
The patent transitions from conventional planar power delivery to a three-dimensional stacked architecture with backside power delivery network layer. The logic die is bonded to the interposer die with the BSPDN layer positioned on the backside, enabling vertical heat dissipation pathways and improving thermal management through spatial reconfiguration of power delivery components.
Solution Approach 2:
The interposer die serves as a thermal intermediary component between the logic die and the heat sink. With higher thermal conductivity than the logic die, the interposer die efficiently conducts heat away from the logic die through the BSPDN layer to the heat sink, acting as a thermal bridge that improves overall heat dissipation performance.
2Reliability
If backside power delivery network layer is added, then heat dissipation is improved, but manufacturing complexity increases
Solution Approach 1:
The semiconductor package is segmented into functionally distinct layers: logic die, interposer die with BSPDN layer, memory dies, and heat sink. This segmentation allows each component to be optimized and manufactured separately using existing processes, then assembled through wafer-level bonding, reducing overall manufacturing complexity despite the advanced architecture.
Solution Approach 2:
The interposer die performs multiple functions simultaneously: it provides the backside power delivery network layer for electrical connectivity, serves as a thermal conduction pathway to the heat sink, and enables mechanical support for the stacked memory dies. This multi-functionality reduces the need for additional specialized components.
3Temperature
If interposer die with higher thermal conductivity is used, then heat dissipation performance increases, but device complexity increases
Solution Approach 1:
The interposer die is designed with locally optimized thermal properties, featuring higher thermal conductivity specifically in the regions requiring heat dissipation. The BSPDN layer is strategically positioned on the backside of the logic die where heat generation is most intense, providing targeted thermal management where it is most needed rather than uniformly across the entire package.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed design enhances heat-dissipation performance and reliability of semiconductor packages by effectively dissipating heat generated in the logic die through the interposer die with superior thermal conductivity, thereby improving the overall package performance.
Implementation Method 1
an interposer die with higher thermal conductivity... effectively dissipating heat generated in the logic die through the interposer die with superior thermal conductivity
Data Source
AI summary
A semiconductor package includes a logic die that includes a backside power delivery network layer, an interposer die disposed on the logic die, a plurality of memory dies stacked on the interposer die, and a mold layer that covers the interposer die and the memory dies. Each of the logic die and the interposer die has a first width.