Backside Power Delivery Layout for Multi-Die Package Protection
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Solution Overview
Problem
Forming connections between substrates in semiconductor devices can cause complications, and existing packaging methods do not effectively address thermal, physical, and electrical protection for integrated circuits.
Innovation Solution
A package architecture featuring backside power delivery networks (BSPDN) with separate signal and power layers on opposite sides of a support circuit, integrated with redistribution layers and connecting elements to facilitate efficient power and signal routing between compute devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If connections are formed between substrates to increase computation, then computational capability is improved, but packaging complexity and difficulty increase
Solution Approach 1:
The support circuit is divided into separate functional layers: a first side with a power layer for electrical power delivery and a second side with a signal network layer for data communication. This segmentation allows independent optimization of power and signal pathways, reducing packaging complexity while maintaining high computational capability through multi-substrate connections
Solution Approach 2:
The patent transitions from planar packaging to three-dimensional stacked architecture with device stacks positioned on opposite sides of a core substrate. Compute devices are arranged in vertical layers (first layer with compute devices, second layer with support circuits), enabling increased computational density without proportionally increasing packaging difficulty
2Productivity
If multiple computational components are integrated in a single unit, then computational power is improved, but thermal management and physical protection become more difficult
Solution Approach 1:
The support circuit separates power delivery functions on the first side from signal processing functions on the second side. This thermal segmentation allows heat-generating compute devices in the first layer to be thermally managed independently from the support circuits in the second layer, facilitating more effective heat dissipation strategies for high-power configurations
Solution Approach 2:
The core substrate acts as an intermediary between device stacks on opposite sides, providing mechanical support and thermal pathways. The core substrate's structure enables heat transfer from compute devices through the substrate to external heat sinks, while maintaining physical protection for the integrated computational components
3Productivity
If substrate connections are formed to enable integrated circuits, then electrical functionality is improved, but connection reliability and protection become more challenging
Solution Approach 1:
The architecture uses vertical stacking with device stacks on both sides of the core substrate connected through three-dimensional pathways. This 3D interconnection approach provides multiple redundant electrical pathways and mechanical attachment points, enhancing connection reliability compared to traditional planar connections while maintaining high electrical functionality
Solution Approach 2:
The first and second device stacks are merged into a single integrated package through the core substrate, with power and signal connections established through the substrate's internal pathways. This merging provides physical protection for all connections within the encapsulated package while maintaining reliable electrical functionality across multiple substrates
Data Source
AI summary
Disclosed herein are methods, systems and devices including a first layer with a first compute device, a second compute device, and a first connecting element, while a second layer has a first support circuit. The first compute device is configured to electrically connect to the second compute device via the first support circuit and the first connecting element. In some embodiments, the first support circuit includes a power layer on a first side of the support circuit, and the first support circuit may include a signal network layer on a second side of the first support circuit, the second side opposite the first side.