Backside Power Line Pitch Layout for BEOL Congestion Relief
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Solution Overview
Problem
The power delivery network in microelectronic devices faces challenges with transistor scaling due to increasing competition for space in the back-end-of-line (BEOL) network, leading to power delivery drops and limited standard cell height scaling, as power and ground rails occupy significant area and cause routing congestion.
Innovation Solution
Implementing a semiconductor structure with a backside power distribution layer featuring two networks of metal lines with different pitches, allowing direct power delivery to standard cells through wider, less resistive lines, decoupling the power delivery network from the signal network and reducing the need for power interconnects in the BEOL stack.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power and ground rails are used in the BEOL network to deliver power to transistors, then power delivery is achieved, but routing congestion increases and standard cell height scaling is limited due to space occupation
Solution Approach 1:
The patent moves the power delivery network from the front-side BEOL stack to the backside of the device, utilizing the backside surface as an additional dimensional space. This allows power rails to be formed on the backside rather than competing for space in the front-side interconnect layers, effectively adding a new dimension for power distribution and eliminating routing congestion in the original BEOL network.
2Productivity
If narrower metal wires and vias are used in the BEOL stack to support transistor scaling, then transistor density increases, but power delivery drop increases due to higher resistance
Solution Approach 1:
The patent segments the power delivery function from the signal interconnect function by creating a separate backside power delivery network. This segmentation allows the front-side BEOL network to focus on signal routing with narrower wires for higher transistor density, while the backside network handles power delivery with wider, lower-resistance paths, eliminating the trade-off between density and power delivery.
3Reliability
If power interconnects are increased to compensate for power delivery drop, then power delivery improves, but device complexity increases due to additional interconnect layers
Solution Approach 1:
The patent extracts the power delivery function from the complex front-side BEOL interconnect architecture and places it on the backside of the device. This extraction simplifies the front-side network by removing power interconnect elements, reducing overall device complexity while maintaining or improving power delivery performance through the dedicated backside power network.
Data Source
AI summary
A semiconductor structure including a device layer, a back end-of-line layer, and a backside power distribution layer. The backside power distribution layer includes a first line network with having a first pitch, and a second line network having a second pitch. The second pitch is greater than the first pitch. In one example, the second pitch is at least 7 times (7×) greater than the first pitch.