Backside Power Plane Layout for Low-Loss IC Power Delivery
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Solution Overview
Problem
The increasing density of integrated circuits leads to power delivery networks becoming a bottleneck due to high resistance and inductance loss, limiting scaling and affecting the performance of transistor devices.
Innovation Solution
A semiconductor structure with a first and second power plane connected via pass through vias, where the first power plane is directly connected to transistor devices and the second power plane is connected through pass through vias, allowing for efficient power delivery with reduced resistance and inductance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If power rails are made larger to deliver higher current, then power delivery capability is improved, but space consumption increases and scaling is limited
Solution Approach 1:
The patent introduces a vertical power delivery dimension by implementing power planes at multiple metal layers (e.g., M1, M2, M3) connected through vias. This multi-layer stacked architecture allows power to be delivered through the third dimension (vertical stacking) rather than solely through horizontal expansion of power rails, enabling higher current delivery without proportionally increasing lateral space consumption in the circuit cell.
2Quantity of substance
If integrated circuit density is increased, then device functionality is improved, but power delivery network resistance and inductance increase
Solution Approach 1:
The patent segments the power delivery network into multiple independent power planes at different metal layers, each serving specific functional blocks or device types. This segmentation allows optimized local power delivery paths for high-density device regions, reducing the total current path length and minimizing cumulative resistance and inductance effects that would otherwise increase with higher device density.
Solution Approach 2:
By distributing power delivery across multiple vertical layers (M1, M2, M3, etc.) connected through vias, the patent creates a three-dimensional power network that reduces the horizontal current path length. This vertical distribution shortens the effective resistance and inductance paths even as device density increases horizontally, mitigating the RL voltage drop problem.
3Power
If power rail size is increased to maintain power distribution, then adequate power delivery is achieved, but circuit cell scalability is reduced
Solution Approach 1:
The multi-layer power plane architecture enables power delivery capacity to scale vertically through additional metal layers rather than requiring proportional horizontal expansion of individual power rails. This allows circuit cells to maintain compact footprints while achieving high power delivery capability through the stacked vertical configuration, preserving scalability as circuits evolve to higher density nodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables more efficient power delivery to transistor devices, reducing resistance and inductance losses, thereby improving the performance and scalability of integrated circuits.
Implementation Method 1
a plurality of pass through vias electrically connecting the second power plane to a second plurality of VBPPs, wherein the plurality of pass through vias pass through the first power plane
Data Source
AI summary
Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a first power plane electrically connected to a first plurality of via-to-backside power planes (VBPPs), a second power plane, and a plurality of pass through vias electrically connecting the second power plane to a second plurality of VBPPs, wherein the plurality of pass through vias pass through the first power plane.