Backside Power Plane in Stacked Vertical FETs
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Solution Overview
Problem
The challenge in semiconductor device technology is the difficulty in electrically coupling layers of vertically stacked field effect transistors (FETs) to a conductive plane due to the compact design and higher density of components, which hinders connectivity and interconnection options, especially when considering the need for electrical insulation.
Innovation Solution
The approach involves forming a via through the semiconductor structure to create a channel for conductive material, using sacrificial materials or insulators to facilitate electrical coupling, and replacing the substrate layer with a metallic ground or power plane to enhance connectivity and interconnection capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertically stacked FETs are used to increase component density, then device integration is improved, but electrical coupling to conductive plane becomes difficult
Solution Approach 1:
The patent introduces a vertical via structure that extends through multiple stacked FET layers to reach the conductive plane, transforming the coupling approach from lateral to vertical dimension. This allows electrical connection through the third dimension (depth) rather than attempting lateral routing in congested planar space, thereby resolving the contradiction between high density and coupling difficulty
Solution Approach 2:
The patent employs a conductive via structure as an intermediary element that bridges the gap between the stacked FET layers and the underlying conductive plane. This intermediary provides a dedicated electrical pathway through the insulating layers and transistor structures, enabling coupling without compromising the vertical stacking architecture
2Area of stationary object
If compact stacked design is implemented, then area efficiency is improved, but interconnection options are reduced
Solution Approach 1:
By routing interconnections vertically through vias rather than laterally through congested planar paths, the patent adds a vertical dimension to the interconnection architecture. This enables multiple connection points and routing options through the vertical stack, increasing interconnection versatility while maintaining compact planar footprint
Solution Approach 2:
The patent segments the interconnection path into discrete vertical via sections that can be independently configured at different stack levels. This segmentation allows flexible routing choices and connection configurations, providing multiple interconnection options despite the compact overall design
Data Source
AI summary
Techniques facilitating forming a backside ground or power plane in stacked vertical transport field effect transistor are provided. A semiconductor structure can include a first field effect transistor (FET). The semiconductor structure can also include a second FET. The first FET can be vertically stacked on a first surface of the second FET. The second FET can be electrically coupled to a conductive plane on a second surface of the second FET, the second surface being opposite to the first surface.