Backside Power Rail Air Gaps for Parasitic Leakage Reduction

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Solution Overview

Problem

In semiconductor integrated circuits, parasitic electrical leakage due to capacitive coupling between input wires and neighboring components leads to logic failures and timing degradation as device sizes shrink, necessitating an improved device structure to address these issues.

Innovation Solution

The introduction of power rails at the backside of the semiconductor device structure with conductive features enclosed by air gaps, which effectively reduce leakage current by minimizing capacitive coupling between conductive features and channel regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If device size is shrunk to increase device density, then productivity is improved, but parasitic electrical leakage increases due to capacitive coupling

Engineering Contradiction:
Improvedevice densityVSAvoidparasitic electrical leakage
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

An air gap is introduced as an intermediary layer between the conductive feature and the channel region. This air gap acts as a mediator that reduces the capacitive coupling between these two structures, thereby reducing parasitic electrical leakage while maintaining the shrunk device dimensions for high device density.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The air gap is selectively positioned only in specific locations where capacitive coupling occurs between conductive features and channel regions. This localized approach reduces parasitic leakage at critical interfaces without affecting the overall device density or requiring global structural changes.

Inventive Principle:
Principle #3Local quality

2Reliability

If air gaps are introduced to reduce parasitic capacitance, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvetiming accuracyVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The air gap is formed by removing material (vacuuming out a sacrificial layer) rather than adding complex structures. This extraction approach creates the necessary isolation space while maintaining a relatively simple overall device architecture, thus improving reliability without proportionally increasing complexity.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The sacrificial layer is deposited and patterned in advance before the final device assembly. This preliminary action allows the air gap to be easily formed by simple removal of the sacrificial material, avoiding the need for complex post-assembly structuring and thereby limiting the increase in device complexity.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enhances the performance of semiconductor devices by reducing parasitic capacitance and leakage currents, thereby improving reliability and timing accuracy.

Implementation Method 1

parasitic electrical leakage may appear in the device due to capacitive coupling formed between an input wire and neighboring components

Methodology Applied
Scientific EffectCapacitive coupling: Capacitance

Data Source

PatentUS20240379761A1Semiconductor device structure integrating air gaps and methods of forming the same
Publication Date: 2024.11.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240379761A1 patent drawing
  • US20240379761A1 patent drawing
  • US20240379761A1 patent drawing

AI summary

A semiconductor device structure, along with methods of forming such, are described. In one embodiment, a semiconductor device structure is provided. The semiconductor device structure includes a substrate having a front side and a back side opposing the front side, a gate stack disposed on the front side of the substrate, a first source/drain feature and a second source/drain feature disposed in opposing sides of the gate stack, wherein each first source/drain feature and second source/drain feature comprises a first side and a second side, and the second side of the first source/drain feature and the back side of the substrate are at different elevations. The semiconductor device structure also includes a conductive feature in contact with the second side of the first source/drain feature, wherein a portion of the back side of the substrate is exposed to air.